| Message ID | 20181029161605.11486-1-palmer@sifive.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add Alistair as a RISC-V Maintainer | expand |
On 29/10/18 17:16, Palmer Dabbelt wrote: > Alistair has been contributing to the RISC-V QEMU port for a while now > so I'd like him to be officially listed as a maintainer. I've checked > with the other RISC-V mainatiners and there are no objectics, and I've "maintainers" "objections" > also checked with Alistair so he knows I'm volunteering him. > > Signed-off-by: Palmer Dabbelt <palmer@sifive.com> FWIW: Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> > --- > MAINTAINERS | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/MAINTAINERS b/MAINTAINERS > index d794bd7a66fe..d550fd8b809c 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -241,6 +241,7 @@ F: disas/ppc.c > RISC-V > M: Michael Clark <mjc@sifive.com> > M: Palmer Dabbelt <palmer@sifive.com> > +M: Alistair Francis <Alistair.Francis@wdc.com> > M: Sagar Karandikar <sagark@eecs.berkeley.edu> > M: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> > S: Maintained >
On Mon, Oct 29, 2018 at 9:44 AM Philippe Mathieu-Daudé <philmd@redhat.com> wrote: > > On 29/10/18 17:16, Palmer Dabbelt wrote: > > Alistair has been contributing to the RISC-V QEMU port for a while now > > so I'd like him to be officially listed as a maintainer. I've checked > > with the other RISC-V mainatiners and there are no objectics, and I've > > "maintainers" "objections" > > > also checked with Alistair so he knows I'm volunteering him. > > > > Signed-off-by: Palmer Dabbelt <palmer@sifive.com> > > FWIW: > Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> I can send a pull request with this patch (and the other RISC-V patch). I'll fix the typos in the PR. Alistair > > > --- > > MAINTAINERS | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git a/MAINTAINERS b/MAINTAINERS > > index d794bd7a66fe..d550fd8b809c 100644 > > --- a/MAINTAINERS > > +++ b/MAINTAINERS > > @@ -241,6 +241,7 @@ F: disas/ppc.c > > RISC-V > > M: Michael Clark <mjc@sifive.com> > > M: Palmer Dabbelt <palmer@sifive.com> > > +M: Alistair Francis <Alistair.Francis@wdc.com> > > M: Sagar Karandikar <sagark@eecs.berkeley.edu> > > M: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> > > S: Maintained > > >
On Mon, 29 Oct 2018 09:30:54 PDT (-0700), philmd@redhat.com wrote: > On 29/10/18 17:16, Palmer Dabbelt wrote: >> Alistair has been contributing to the RISC-V QEMU port for a while now >> so I'd like him to be officially listed as a maintainer. I've checked >> with the other RISC-V mainatiners and there are no objectics, and I've > > "maintainers" "objections" Ah, thanks -- I guess the first email I write it the morning shouldn't go out in public :). > >> also checked with Alistair so he knows I'm volunteering him. >> >> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> > > FWIW: > Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> > >> --- >> MAINTAINERS | 1 + >> 1 file changed, 1 insertion(+) >> >> diff --git a/MAINTAINERS b/MAINTAINERS >> index d794bd7a66fe..d550fd8b809c 100644 >> --- a/MAINTAINERS >> +++ b/MAINTAINERS >> @@ -241,6 +241,7 @@ F: disas/ppc.c >> RISC-V >> M: Michael Clark <mjc@sifive.com> >> M: Palmer Dabbelt <palmer@sifive.com> >> +M: Alistair Francis <Alistair.Francis@wdc.com> >> M: Sagar Karandikar <sagark@eecs.berkeley.edu> >> M: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> >> S: Maintained >>
On Mon, 29 Oct 2018 09:48:30 PDT (-0700), alistair23@gmail.com wrote: > On Mon, Oct 29, 2018 at 9:44 AM Philippe Mathieu-Daudé > <philmd@redhat.com> wrote: >> >> On 29/10/18 17:16, Palmer Dabbelt wrote: >> > Alistair has been contributing to the RISC-V QEMU port for a while now >> > so I'd like him to be officially listed as a maintainer. I've checked >> > with the other RISC-V mainatiners and there are no objectics, and I've >> >> "maintainers" "objections" >> >> > also checked with Alistair so he knows I'm volunteering him. >> > >> > Signed-off-by: Palmer Dabbelt <palmer@sifive.com> >> >> FWIW: >> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> > > Reviewed-by: Alistair Francis <alistair.francis@wdc.com> > > I can send a pull request with this patch (and the other RISC-V > patch). I'll fix the typos in the PR. I don't think we have anything ready to go right now: your PCIe patches still have some outstanding feedback (on interrupt stuff), and Bastian's decodetree stuff has some patches from Richard Henderson that should be merged in. I was hoping to get through reviewing Michael's patches to fix the FS dirty bit, but haven't had time yet -- they're tested, but I haven't actually read through them. Maybe we should get a RISC-V QEMU mailing list so we can keep everyone in sync without spamming the whole world? > > Alistair > >> >> > --- >> > MAINTAINERS | 1 + >> > 1 file changed, 1 insertion(+) >> > >> > diff --git a/MAINTAINERS b/MAINTAINERS >> > index d794bd7a66fe..d550fd8b809c 100644 >> > --- a/MAINTAINERS >> > +++ b/MAINTAINERS >> > @@ -241,6 +241,7 @@ F: disas/ppc.c >> > RISC-V >> > M: Michael Clark <mjc@sifive.com> >> > M: Palmer Dabbelt <palmer@sifive.com> >> > +M: Alistair Francis <Alistair.Francis@wdc.com> >> > M: Sagar Karandikar <sagark@eecs.berkeley.edu> >> > M: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> >> > S: Maintained >> > >>
On Mon, Oct 29, 2018 at 10:14 AM Palmer Dabbelt <palmer@sifive.com> wrote: > > On Mon, 29 Oct 2018 09:48:30 PDT (-0700), alistair23@gmail.com wrote: > > On Mon, Oct 29, 2018 at 9:44 AM Philippe Mathieu-Daudé > > <philmd@redhat.com> wrote: > >> > >> On 29/10/18 17:16, Palmer Dabbelt wrote: > >> > Alistair has been contributing to the RISC-V QEMU port for a while now > >> > so I'd like him to be officially listed as a maintainer. I've checked > >> > with the other RISC-V mainatiners and there are no objectics, and I've > >> > >> "maintainers" "objections" > >> > >> > also checked with Alistair so he knows I'm volunteering him. > >> > > >> > Signed-off-by: Palmer Dabbelt <palmer@sifive.com> > >> > >> FWIW: > >> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> > > > > Reviewed-by: Alistair Francis <alistair.francis@wdc.com> > > > > I can send a pull request with this patch (and the other RISC-V > > patch). I'll fix the typos in the PR. > > I don't think we have anything ready to go right now: your PCIe patches still > have some outstanding feedback (on interrupt stuff), and Bastian's decodetree > stuff has some patches from Richard Henderson that should be merged in. I was > hoping to get through reviewing Michael's patches to fix the FS dirty bit, but > haven't had time yet -- they're tested, but I haven't actually read through > them. Dayeol Lee's patch "target/riscv/pmp.c: pmpcfg_csr_read returns bogus value on RV64" is ready to be applied. It's probably too close to soft freeze for anything else to make it in for 3.1. > > Maybe we should get a RISC-V QEMU mailing list so we can keep everyone in sync > without spamming the whole world? We can, but I don't think we have that much traffic at the moment. Alistair > > > > > Alistair > > > >> > >> > --- > >> > MAINTAINERS | 1 + > >> > 1 file changed, 1 insertion(+) > >> > > >> > diff --git a/MAINTAINERS b/MAINTAINERS > >> > index d794bd7a66fe..d550fd8b809c 100644 > >> > --- a/MAINTAINERS > >> > +++ b/MAINTAINERS > >> > @@ -241,6 +241,7 @@ F: disas/ppc.c > >> > RISC-V > >> > M: Michael Clark <mjc@sifive.com> > >> > M: Palmer Dabbelt <palmer@sifive.com> > >> > +M: Alistair Francis <Alistair.Francis@wdc.com> > >> > M: Sagar Karandikar <sagark@eecs.berkeley.edu> > >> > M: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> > >> > S: Maintained > >> > > >>
On 29 October 2018 at 17:14, Palmer Dabbelt <palmer@sifive.com> wrote: > I don't think we have anything ready to go right now: your PCIe patches > still have some outstanding feedback (on interrupt stuff), and Bastian's > decodetree stuff has some patches from Richard Henderson that should be > merged in. I was hoping to get through reviewing Michael's patches to fix > the FS dirty bit, but haven't had time yet -- they're tested, but I haven't > actually read through them. > > Maybe we should get a RISC-V QEMU mailing list so we can keep everyone in > sync without spamming the whole world? We can sort out a qemu-riscv mailing list like the ones we have for ppc and arm if you like: https://wiki.qemu.org/Contribute/MailingLists Our general principle is that all posts should cc qemu-devel as well as the subsystem list; the idea is that if you only care about riscv you can just subscribe to the lower volume list, but people on qemu-devel still get to see everything without having to subscribe to half a dozen different other lists. NB: softfreeze is tomorrow, which is our deadline by which any pull requests for new feature work should be on the mailing list. After that it's bugfixes only. So my feeling is that both the decodetree and the PCI patches have missed the boat for 3.1 and can be dealt with in a more leisurely timescale. If you have bugfixes in your tree that could do with being upstreamed, this is a good time in the release cycle to look at doing that, I think. thanks -- PMM
On Mon, 29 Oct 2018 10:59:47 PDT (-0700), Peter Maydell wrote: > On 29 October 2018 at 17:14, Palmer Dabbelt <palmer@sifive.com> wrote: >> I don't think we have anything ready to go right now: your PCIe patches >> still have some outstanding feedback (on interrupt stuff), and Bastian's >> decodetree stuff has some patches from Richard Henderson that should be >> merged in. I was hoping to get through reviewing Michael's patches to fix >> the FS dirty bit, but haven't had time yet -- they're tested, but I haven't >> actually read through them. >> >> Maybe we should get a RISC-V QEMU mailing list so we can keep everyone in >> sync without spamming the whole world? > > We can sort out a qemu-riscv mailing list like the ones we have > for ppc and arm if you like: > https://wiki.qemu.org/Contribute/MailingLists I think that'd be good. It makes things a bit easier on my end as I can ensure I don't miss any patches that end up on our list. > Our general principle is that all posts should cc qemu-devel as > well as the subsystem list; the idea is that if you only care > about riscv you can just subscribe to the lower volume list, but > people on qemu-devel still get to see everything without having > to subscribe to half a dozen different other lists. OK, that's fine. > NB: softfreeze is tomorrow, which is our deadline by which any > pull requests for new feature work should be on the mailing list. > After that it's bugfixes only. So my feeling is that both the > decodetree and the PCI patches have missed the boat for 3.1 > and can be dealt with in a more leisurely timescale. Makes sense. > If you have bugfixes in your tree that could do with being > upstreamed, this is a good time in the release cycle to look > at doing that, I think. We have a big bugfix list, but it's all intermingled with new features in one tree. I'm working through sorting this out, with the hope being that we don't have any major known bugs in 3.1 -- that's my biggest worry, as I'd really like to have the QEMU shipped by distros actually work. > > thanks > -- PMM
On 29 October 2018 at 18:41, Palmer Dabbelt <palmer@sifive.com> wrote: > On Mon, 29 Oct 2018 10:59:47 PDT (-0700), Peter Maydell wrote: >> >> On 29 October 2018 at 17:14, Palmer Dabbelt <palmer@sifive.com> wrote: >>> >>> I don't think we have anything ready to go right now: your PCIe patches >>> still have some outstanding feedback (on interrupt stuff), and Bastian's >>> decodetree stuff has some patches from Richard Henderson that should be >>> merged in. I was hoping to get through reviewing Michael's patches to >>> fix >>> the FS dirty bit, but haven't had time yet -- they're tested, but I >>> haven't >>> actually read through them. >>> >>> Maybe we should get a RISC-V QEMU mailing list so we can keep everyone in >>> sync without spamming the whole world? >> >> >> We can sort out a qemu-riscv mailing list like the ones we have >> for ppc and arm if you like: >> https://wiki.qemu.org/Contribute/MailingLists > > > I think that'd be good. It makes things a bit easier on my end as I can > ensure I don't miss any patches that end up on our list. OK, I have set one up. The subscription page is at: https://lists.nongnu.org/mailman/listinfo/qemu-riscv I think I have got the list config correct but let me know if you notice anything weird. I suggest submitting a patch to MAINTAINERS that adds an L: qemu-riscv@nongnu.org line to the RISC-V section of that file. thanks -- PMM
On Tue, Oct 30, 2018 at 4:04 PM Peter Maydell <peter.maydell@linaro.org> wrote: > > On 29 October 2018 at 18:41, Palmer Dabbelt <palmer@sifive.com> wrote: > > On Mon, 29 Oct 2018 10:59:47 PDT (-0700), Peter Maydell wrote: > >> > >> On 29 October 2018 at 17:14, Palmer Dabbelt <palmer@sifive.com> wrote: > >>> > >>> I don't think we have anything ready to go right now: your PCIe patches > >>> still have some outstanding feedback (on interrupt stuff), and Bastian's > >>> decodetree stuff has some patches from Richard Henderson that should be > >>> merged in. I was hoping to get through reviewing Michael's patches to > >>> fix > >>> the FS dirty bit, but haven't had time yet -- they're tested, but I > >>> haven't > >>> actually read through them. > >>> > >>> Maybe we should get a RISC-V QEMU mailing list so we can keep everyone in > >>> sync without spamming the whole world? > >> > >> > >> We can sort out a qemu-riscv mailing list like the ones we have > >> for ppc and arm if you like: > >> https://wiki.qemu.org/Contribute/MailingLists > > > > > > I think that'd be good. It makes things a bit easier on my end as I can > > ensure I don't miss any patches that end up on our list. > > OK, I have set one up. The subscription page is at: > https://lists.nongnu.org/mailman/listinfo/qemu-riscv Thanks! > I think I have got the list config correct but let me know if you > notice anything weird. http://lists.nongnu.org/archive/html/qemu-riscv/ returns 404 Not found: The requested URL /archive/html/qemu-riscv/ was not found on this server. This might be a cron job and I need to wait. > > I suggest submitting a patch to MAINTAINERS that adds an > L: qemu-riscv@nongnu.org > line to the RISC-V section of that file. > > thanks > -- PMM >
On 30 October 2018 at 17:54, Philippe Mathieu-Daudé <philippe@mathieu-daude.net> wrote: > http://lists.nongnu.org/archive/html/qemu-riscv/ returns 404 Not > found: The requested URL /archive/html/qemu-riscv/ was not found on > this server. > > This might be a cron job and I need to wait. Yeah, it will do that until the archive populates, I think. thanks -- PMM
On 30 October 2018 at 17:56, Peter Maydell <peter.maydell@linaro.org> wrote: > On 30 October 2018 at 17:54, Philippe Mathieu-Daudé > <philippe@mathieu-daude.net> wrote: >> http://lists.nongnu.org/archive/html/qemu-riscv/ returns 404 Not >> found: The requested URL /archive/html/qemu-riscv/ was not found on >> this server. >> >> This might be a cron job and I need to wait. > > Yeah, it will do that until the archive populates, I think. ...which it now has. thanks -- PMM
diff --git a/MAINTAINERS b/MAINTAINERS index d794bd7a66fe..d550fd8b809c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -241,6 +241,7 @@ F: disas/ppc.c RISC-V M: Michael Clark <mjc@sifive.com> M: Palmer Dabbelt <palmer@sifive.com> +M: Alistair Francis <Alistair.Francis@wdc.com> M: Sagar Karandikar <sagark@eecs.berkeley.edu> M: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> S: Maintained
Alistair has been contributing to the RISC-V QEMU port for a while now so I'd like him to be officially listed as a maintainer. I've checked with the other RISC-V mainatiners and there are no objectics, and I've also checked with Alistair so he knows I'm volunteering him. Signed-off-by: Palmer Dabbelt <palmer@sifive.com> --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+)