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DIR:OUT; SFP:1102; SCL:1; SRVR:DM6PR01MB3673; H:DM6PR01MB4825.prod.exchangelabs.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:0; MX:1; received-spf: None (protection.outlook.com: os.amperecomputing.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: nd8edYer/Os8EmbDBka/hCzWhCUtf/meGG+f0L/nW6EFcYBM0oTsJkclLFewY2GEpJzb7U80n/ZtVQ4zhkS2oJKY01efHcHP9zo0e+wh28syh3KLwIfN80PX0+cScQ5UyrKWCtNnLIC7Z3dj9dciSKoqSB4q+GE0OpuSWCay62aoawsgKvGEQGMZ9tz64pcCpX8WfxKLbAz47K99jCRYS1eOgze96MEQPqNI9vloW9zWHKt45Gb3xzyZvNFh37XiJnCombz0URRM1AnzcX0yqBxuNl/N5A7qQ4XqQNtYO+Ye5oTmh0PzQ3Ek/7JvbPGftaY7Im7CSeaTvwh+zoBoSDPw0vl7zQC9iX1r/kkwTxY= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: os.amperecomputing.com X-MS-Exchange-CrossTenant-Network-Message-Id: 1e9983aa-fff3-456f-777c-08d6434fc06e X-MS-Exchange-CrossTenant-originalarrivaltime: 05 Nov 2018 18:51:53.0757 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3bc2b170-fd94-476d-b0ce-4229bdc904a7 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR01MB3673 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 40.107.74.130 Subject: [Qemu-devel] [PATCH v7 03/12] target/arm: Swap PMU values before/after migrations X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aaron Lindsay , Aaron Lindsay , Michael Spradling , "qemu-devel@nongnu.org" , Digant Desai Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Because of the PMU's design, many register accesses have side effects which are inter-related, meaning that the normal method of saving CP registers can result in inconsistent state. These side-effects are largely handled in pmu_op_start/finish functions which can be called before and after the state is saved/restored. By doing this and adding raw read/write functions for the affected registers, we avoid migration-related inconsistencies. Signed-off-by: Aaron Lindsay --- target/arm/helper.c | 6 ++++-- target/arm/machine.c | 20 ++++++++++++++++++++ 2 files changed, 24 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 281bcff1da..5deff3d11f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1450,11 +1450,13 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 0, .access = PL0_RW, .accessfn = pmreg_access_ccntr, .type = ARM_CP_IO, - .readfn = pmccntr_read, .writefn = pmccntr_write, }, + .fieldoffset = offsetof(CPUARMState, cp15.c15_ccnt), + .readfn = pmccntr_read, .writefn = pmccntr_write, + .raw_readfn = raw_read, .raw_writefn = raw_write, }, #endif { .name = "PMCCFILTR_EL0", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 15, .opc2 = 7, - .writefn = pmccfiltr_write, + .writefn = pmccfiltr_write, .raw_writefn = raw_write, .access = PL0_RW, .accessfn = pmreg_access, .type = ARM_CP_IO, .fieldoffset = offsetof(CPUARMState, cp15.pmccfiltr_el0), diff --git a/target/arm/machine.c b/target/arm/machine.c index 239fe4e84d..6d14b08e0c 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -604,6 +604,8 @@ static int cpu_pre_save(void *opaque) { ARMCPU *cpu = opaque; + pmu_op_start(&cpu->env); + if (kvm_enabled()) { if (!write_kvmstate_to_list(cpu)) { /* This should never fail */ @@ -625,6 +627,20 @@ static int cpu_pre_save(void *opaque) return 0; } +static int cpu_post_save(void *opaque) +{ + ARMCPU *cpu = opaque; + pmu_op_finish(&cpu->env); + return 0; +} + +static int cpu_pre_load(void *opaque) +{ + ARMCPU *cpu = opaque; + pmu_op_start(&cpu->env); + return 0; +} + static int cpu_post_load(void *opaque, int version_id) { ARMCPU *cpu = opaque; @@ -672,6 +688,8 @@ static int cpu_post_load(void *opaque, int version_id) hw_breakpoint_update_all(cpu); hw_watchpoint_update_all(cpu); + pmu_op_finish(&cpu->env); + return 0; } @@ -680,6 +698,8 @@ const VMStateDescription vmstate_arm_cpu = { .version_id = 22, .minimum_version_id = 22, .pre_save = cpu_pre_save, + .post_save = cpu_post_save, + .pre_load = cpu_pre_load, .post_load = cpu_post_load, .fields = (VMStateField[]) { VMSTATE_UINT32_ARRAY(env.regs, ARMCPU, 16),