From patchwork Tue Nov 13 23:50:45 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 10681661 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A51B7139B for ; Tue, 13 Nov 2018 23:52:56 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 981842B5D8 for ; Tue, 13 Nov 2018 23:52:55 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8C51D2B5E5; Tue, 13 Nov 2018 23:52:55 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 167EC2B5DA for ; Tue, 13 Nov 2018 23:52:55 +0000 (UTC) Received: from localhost ([::1]:56538 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gMiUI-0004Uu-9u for patchwork-qemu-devel@patchwork.kernel.org; Tue, 13 Nov 2018 18:52:54 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51480) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gMiT4-0003b3-Nr for qemu-devel@nongnu.org; Tue, 13 Nov 2018 18:51:43 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gMiT2-0006hU-NT for qemu-devel@nongnu.org; Tue, 13 Nov 2018 18:51:38 -0500 Received: from mail-pl1-x643.google.com ([2607:f8b0:4864:20::643]:39174) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gMiSx-0006ae-OF for qemu-devel@nongnu.org; Tue, 13 Nov 2018 18:51:34 -0500 Received: by mail-pl1-x643.google.com with SMTP id b5-v6so6815050pla.6 for ; Tue, 13 Nov 2018 15:51:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=subject:date:message-id:in-reply-to:references:cc:from:to; bh=jiJQ+JOIMV0I2GJ3MV1g+OOMPgoMF7Rval6G4QIiJEo=; b=QkhHVdjwgtGGWGUd1dLi8WNBR+H5NZ/x1xjM86786xmx555L12jnK+N7FntYwhAchb PiuDK5crQYQcwrgU8ElnQsZx9IwYSUM0el9Xs1fKdhB9Hp5QfJQ8itJ1VpvaipCcQ7vS ivCUjyEvhXoI+7XoM1LhPgRyqC9Wf7z2YnIOkWcFBKpGop9rrsz4ctHwLSfihD4637/v AYB7uWI9cqNZD8qk2jc8h73ujCDGmRo11nYR6z8hRwZbiuEyXv53MZjtF2Rl9as/aoR/ 9ehSL/yp7Za9vbWPLI9Cen3pcDtJef8MRapJDBXGdeXQZKgwmrapT/ziT06uau16OXss uugA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:date:message-id:in-reply-to:references :cc:from:to; bh=jiJQ+JOIMV0I2GJ3MV1g+OOMPgoMF7Rval6G4QIiJEo=; b=MvcXsWNo0suP9gqZADeKxr3dTumYTSphXlzT6mrUwyHMFVQXkFmoXiocwYB077LN2X 68D2LHz0lpBVPJy0l40hbiT+el6jZxOgh+MSo75clOatdclPevwj5j7XSQMH7fkXZyC1 A8b1mHRmfda18dSzbUqrx6Ia7o1apwRVvThYIL3XRW5EnWkhDVo0V0h8BMPLoC5qynBq g0XFFQBa9Z08jTay7kcKV8H7UrsDa0lIrqrJ8TCXIk8r5pHSR9ie5cBaCt2UTTsP0AXO 9/AE/zFqzTYMQrv/F57KK/rolZWRLWEaauVxsg7gUzb2JRKXNz7x9AXnTA8U7kz09IxF 2vPA== X-Gm-Message-State: AGRZ1gLrBxjhwLg2Xqgvjex44LS9oRIFaSiv3w6UmJe0OTi36wDjznYR obQeyWcCpgD8hRGyp5Tor1kJ/ija0jemVA== X-Google-Smtp-Source: AJdET5fOfG7Gum2pl418WZGURlWpvspf1CkdOB0jOOdFKTtoqHcey6MnQgkTgbs65ObdDIRC5Gsilw== X-Received: by 2002:a17:902:2ac3:: with SMTP id j61mr2840766plb.185.1542153084393; Tue, 13 Nov 2018 15:51:24 -0800 (PST) Received: from localhost ([64.114.255.114]) by smtp.gmail.com with ESMTPSA id y25-v6sm99114pfa.136.2018.11.13.15.51.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 13 Nov 2018 15:51:23 -0800 (PST) Date: Tue, 13 Nov 2018 15:50:45 -0800 Message-Id: <20181113235045.14155-5-palmer@sifive.com> X-Mailer: git-send-email 2.18.1 In-Reply-To: <20181113235045.14155-1-palmer@sifive.com> References: <20181113235045.14155-1-palmer@sifive.com> From: Palmer Dabbelt To: qemu-riscv@nongnu.org X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PULL 4/4] RISC-V: Respect fences for user-only emulators X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Palmer Dabbelt , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Our current fence implementation ignores fences for the user-only configurations. This is incorrect but unlikely to manifest: it requires multi-threaded user-only code that takes advantage of the weakness in the host's memory model and can be inlined by TCG. This patch simply treats fences the same way for all our emulators. I've given it to testing as I don't want to construct a test that would actually trigger the failure. Our fence implementation has an additional deficiency where we map all RISC-V fences to full fences. Now that we have a formal memory model for RISC-V we can start to take advantage of the strength bits on our fence instructions. This requires a bit more though, so I'm going to split it out because the implementation is still correct without taking advantage of these weaker fences. Thanks to Richard Henderson for pointing out both of the issues. Signed-off-by: Palmer Dabbelt Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson Reviewed-by: Michael Clark --- target/riscv/translate.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index f44eb9c41b48..312bf298b3c2 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1776,7 +1776,6 @@ static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx) GET_RM(ctx->opcode)); break; case OPC_RISC_FENCE: -#ifndef CONFIG_USER_ONLY if (ctx->opcode & 0x1000) { /* FENCE_I is a no-op in QEMU, * however we need to end the translation block */ @@ -1787,7 +1786,6 @@ static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx) /* FENCE is a full memory barrier. */ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); } -#endif break; case OPC_RISC_SYSTEM: gen_system(env, ctx, MASK_OP_SYSTEM(ctx->opcode), rd, rs1,