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[for-4.0,v2,01/37] tcg/i386: Always use %ebp for TCG_AREG0

Message ID 20181123144558.5048-2-richard.henderson@linaro.org (mailing list archive)
State New, archived
Headers show
Series tcg: Assorted cleanups | expand

Commit Message

Richard Henderson Nov. 23, 2018, 2:45 p.m. UTC
For x86_64, this can result in smaller code when manipulating
TCG_TYPE_I32, as we can omit a REX prefix.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/i386/tcg-target.h | 8 ++------
 1 file changed, 2 insertions(+), 6 deletions(-)

Comments

Alex Bennée Nov. 29, 2018, 12:52 p.m. UTC | #1
Richard Henderson <richard.henderson@linaro.org> writes:

> For x86_64, this can result in smaller code when manipulating
> TCG_TYPE_I32, as we can omit a REX prefix.

I take it you mean passing TCG_TYPE_I32 back and forth from the register
backing store in CPUEnv which TCG_AREG0 points at?

Anyway:

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>


>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  tcg/i386/tcg-target.h | 8 ++------
>  1 file changed, 2 insertions(+), 6 deletions(-)
>
> diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
> index 9fdf37f23c..7488c3d869 100644
> --- a/tcg/i386/tcg-target.h
> +++ b/tcg/i386/tcg-target.h
> @@ -84,6 +84,8 @@ typedef enum {
>      TCG_REG_RBP = TCG_REG_EBP,
>      TCG_REG_RSI = TCG_REG_ESI,
>      TCG_REG_RDI = TCG_REG_EDI,
> +
> +    TCG_AREG0 = TCG_REG_EBP,
>  } TCGReg;
>
>  /* used for function call generation */
> @@ -194,12 +196,6 @@ extern bool have_avx2;
>  #define TCG_TARGET_extract_i64_valid(ofs, len) \
>      (((ofs) == 8 && (len) == 8) || ((ofs) + (len)) == 32)
>
> -#if TCG_TARGET_REG_BITS == 64
> -# define TCG_AREG0 TCG_REG_R14
> -#else
> -# define TCG_AREG0 TCG_REG_EBP
> -#endif
> -
>  static inline void flush_icache_range(uintptr_t start, uintptr_t stop)
>  {
>  }


--
Alex Bennée
Richard Henderson Nov. 29, 2018, 2:55 p.m. UTC | #2
On 11/29/18 4:52 AM, Alex Bennée wrote:
> 
> Richard Henderson <richard.henderson@linaro.org> writes:
> 
>> For x86_64, this can result in smaller code when manipulating
>> TCG_TYPE_I32, as we can omit a REX prefix.
> 
> I take it you mean passing TCG_TYPE_I32 back and forth from the register
> backing store in CPUEnv which TCG_AREG0 points at?

Yes, exactly.  Perhaps I should expand my comment...


r~
diff mbox series

Patch

diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index 9fdf37f23c..7488c3d869 100644
--- a/tcg/i386/tcg-target.h
+++ b/tcg/i386/tcg-target.h
@@ -84,6 +84,8 @@  typedef enum {
     TCG_REG_RBP = TCG_REG_EBP,
     TCG_REG_RSI = TCG_REG_ESI,
     TCG_REG_RDI = TCG_REG_EDI,
+
+    TCG_AREG0 = TCG_REG_EBP,
 } TCGReg;
 
 /* used for function call generation */
@@ -194,12 +196,6 @@  extern bool have_avx2;
 #define TCG_TARGET_extract_i64_valid(ofs, len) \
     (((ofs) == 8 && (len) == 8) || ((ofs) + (len)) == 32)
 
-#if TCG_TARGET_REG_BITS == 64
-# define TCG_AREG0 TCG_REG_R14
-#else
-# define TCG_AREG0 TCG_REG_EBP
-#endif
-
 static inline void flush_icache_range(uintptr_t start, uintptr_t stop)
 {
 }