diff mbox series

[v6,09/13] hardfloat: implement float32/64 multiplication

Message ID 20181124235553.17371-10-cota@braap.org (mailing list archive)
State New, archived
Headers show
Series hardfloat | expand

Commit Message

Emilio Cota Nov. 24, 2018, 11:55 p.m. UTC 
Performance results for fp-bench:

1. Intel(R) Core(TM) i7-6700K CPU @ 4.00GHz
- before:
mul-single: 126.91 MFlops
mul-double: 118.28 MFlops
- after:
mul-single: 258.02 MFlops
mul-double: 197.96 MFlops

2. ARM Aarch64 A57 @ 2.4GHz
- before:
mul-single: 37.42 MFlops
mul-double: 38.77 MFlops
- after:
mul-single: 73.41 MFlops
mul-double: 76.93 MFlops

3. IBM POWER8E @ 2.1 GHz
- before:
mul-single: 58.40 MFlops
mul-double: 59.33 MFlops
- after:
mul-single: 60.25 MFlops
mul-double: 94.79 MFlops

Signed-off-by: Emilio G. Cota <cota@braap.org>
---
 fpu/softfloat.c | 54 +++++++++++++++++++++++++++++++++++++++++++++++--
 1 file changed, 52 insertions(+), 2 deletions(-)

Comments

Alex Bennée Dec. 5, 2018, 10:10 a.m. UTC | #1 
Emilio G. Cota <cota@braap.org> writes:

> Performance results for fp-bench:
>
> 1. Intel(R) Core(TM) i7-6700K CPU @ 4.00GHz
> - before:
> mul-single: 126.91 MFlops
> mul-double: 118.28 MFlops
> - after:
> mul-single: 258.02 MFlops
> mul-double: 197.96 MFlops
>
> 2. ARM Aarch64 A57 @ 2.4GHz
> - before:
> mul-single: 37.42 MFlops
> mul-double: 38.77 MFlops
> - after:
> mul-single: 73.41 MFlops
> mul-double: 76.93 MFlops
>
> 3. IBM POWER8E @ 2.1 GHz
> - before:
> mul-single: 58.40 MFlops
> mul-double: 59.33 MFlops
> - after:
> mul-single: 60.25 MFlops
> mul-double: 94.79 MFlops
>
> Signed-off-by: Emilio G. Cota <cota@braap.org>

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

> ---
>  fpu/softfloat.c | 54 +++++++++++++++++++++++++++++++++++++++++++++++--
>  1 file changed, 52 insertions(+), 2 deletions(-)
>
> diff --git a/fpu/softfloat.c b/fpu/softfloat.c
> index cc500b1618..58e67d9b80 100644
> --- a/fpu/softfloat.c
> +++ b/fpu/softfloat.c
> @@ -1232,7 +1232,8 @@ float16 QEMU_FLATTEN float16_mul(float16 a, float16 b, float_status *status)
>      return float16_round_pack_canonical(pr, status);
>  }
>
> -float32 QEMU_FLATTEN float32_mul(float32 a, float32 b, float_status *status)
> +static float32 QEMU_SOFTFLOAT_ATTR
> +soft_f32_mul(float32 a, float32 b, float_status *status)
>  {
>      FloatParts pa = float32_unpack_canonical(a, status);
>      FloatParts pb = float32_unpack_canonical(b, status);
> @@ -1241,7 +1242,8 @@ float32 QEMU_FLATTEN float32_mul(float32 a, float32 b, float_status *status)
>      return float32_round_pack_canonical(pr, status);
>  }
>
> -float64 QEMU_FLATTEN float64_mul(float64 a, float64 b, float_status *status)
> +static float64 QEMU_SOFTFLOAT_ATTR
> +soft_f64_mul(float64 a, float64 b, float_status *status)
>  {
>      FloatParts pa = float64_unpack_canonical(a, status);
>      FloatParts pb = float64_unpack_canonical(b, status);
> @@ -1250,6 +1252,54 @@ float64 QEMU_FLATTEN float64_mul(float64 a, float64 b, float_status *status)
>      return float64_round_pack_canonical(pr, status);
>  }
>
> +static float hard_f32_mul(float a, float b)
> +{
> +    return a * b;
> +}
> +
> +static double hard_f64_mul(double a, double b)
> +{
> +    return a * b;
> +}
> +
> +static bool f32_mul_fast_test(union_float32 a, union_float32 b)
> +{
> +    return float32_is_zero(a.s) || float32_is_zero(b.s);
> +}
> +
> +static bool f64_mul_fast_test(union_float64 a, union_float64 b)
> +{
> +    return float64_is_zero(a.s) || float64_is_zero(b.s);
> +}
> +
> +static float32 f32_mul_fast_op(float32 a, float32 b, float_status *s)
> +{
> +    bool signbit = float32_is_neg(a) ^ float32_is_neg(b);
> +
> +    return float32_set_sign(float32_zero, signbit);
> +}
> +
> +static float64 f64_mul_fast_op(float64 a, float64 b, float_status *s)
> +{
> +    bool signbit = float64_is_neg(a) ^ float64_is_neg(b);
> +
> +    return float64_set_sign(float64_zero, signbit);
> +}
> +
> +float32 QEMU_FLATTEN
> +float32_mul(float32 a, float32 b, float_status *s)
> +{
> +    return float32_gen2(a, b, s, hard_f32_mul, soft_f32_mul,
> +                        f32_is_zon2, NULL, f32_mul_fast_test, f32_mul_fast_op);
> +}
> +
> +float64 QEMU_FLATTEN
> +float64_mul(float64 a, float64 b, float_status *s)
> +{
> +    return float64_gen2(a, b, s, hard_f64_mul, soft_f64_mul,
> +                        f64_is_zon2, NULL, f64_mul_fast_test, f64_mul_fast_op);
> +}
> +
>  /*
>   * Returns the result of multiplying the floating-point values `a' and
>   * `b' then adding 'c', with no intermediate rounding step after the


--
Alex Bennée
diff mbox series

Patch

diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index cc500b1618..58e67d9b80 100644
--- a/fpu/softfloat.c
+++ b/fpu/softfloat.c
@@ -1232,7 +1232,8 @@  float16 QEMU_FLATTEN float16_mul(float16 a, float16 b, float_status *status)
     return float16_round_pack_canonical(pr, status);
 }
 
-float32 QEMU_FLATTEN float32_mul(float32 a, float32 b, float_status *status)
+static float32 QEMU_SOFTFLOAT_ATTR
+soft_f32_mul(float32 a, float32 b, float_status *status)
 {
     FloatParts pa = float32_unpack_canonical(a, status);
     FloatParts pb = float32_unpack_canonical(b, status);
@@ -1241,7 +1242,8 @@  float32 QEMU_FLATTEN float32_mul(float32 a, float32 b, float_status *status)
     return float32_round_pack_canonical(pr, status);
 }
 
-float64 QEMU_FLATTEN float64_mul(float64 a, float64 b, float_status *status)
+static float64 QEMU_SOFTFLOAT_ATTR
+soft_f64_mul(float64 a, float64 b, float_status *status)
 {
     FloatParts pa = float64_unpack_canonical(a, status);
     FloatParts pb = float64_unpack_canonical(b, status);
@@ -1250,6 +1252,54 @@  float64 QEMU_FLATTEN float64_mul(float64 a, float64 b, float_status *status)
     return float64_round_pack_canonical(pr, status);
 }
 
+static float hard_f32_mul(float a, float b)
+{
+    return a * b;
+}
+
+static double hard_f64_mul(double a, double b)
+{
+    return a * b;
+}
+
+static bool f32_mul_fast_test(union_float32 a, union_float32 b)
+{
+    return float32_is_zero(a.s) || float32_is_zero(b.s);
+}
+
+static bool f64_mul_fast_test(union_float64 a, union_float64 b)
+{
+    return float64_is_zero(a.s) || float64_is_zero(b.s);
+}
+
+static float32 f32_mul_fast_op(float32 a, float32 b, float_status *s)
+{
+    bool signbit = float32_is_neg(a) ^ float32_is_neg(b);
+
+    return float32_set_sign(float32_zero, signbit);
+}
+
+static float64 f64_mul_fast_op(float64 a, float64 b, float_status *s)
+{
+    bool signbit = float64_is_neg(a) ^ float64_is_neg(b);
+
+    return float64_set_sign(float64_zero, signbit);
+}
+
+float32 QEMU_FLATTEN
+float32_mul(float32 a, float32 b, float_status *s)
+{
+    return float32_gen2(a, b, s, hard_f32_mul, soft_f32_mul,
+                        f32_is_zon2, NULL, f32_mul_fast_test, f32_mul_fast_op);
+}
+
+float64 QEMU_FLATTEN
+float64_mul(float64 a, float64 b, float_status *s)
+{
+    return float64_gen2(a, b, s, hard_f64_mul, soft_f64_mul,
+                        f64_is_zon2, NULL, f64_mul_fast_test, f64_mul_fast_op);
+}
+
 /*
  * Returns the result of multiplying the floating-point values `a' and
  * `b' then adding 'c', with no intermediate rounding step after the