From patchwork Fri Dec 14 03:19:10 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 10730415 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C04FA6C5 for ; Fri, 14 Dec 2018 03:29:34 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B0CE72CF74 for ; Fri, 14 Dec 2018 03:29:34 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A23DF2CF75; Fri, 14 Dec 2018 03:29:34 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 489342CF7F for ; Fri, 14 Dec 2018 03:29:34 +0000 (UTC) Received: from localhost ([::1]:59107 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXeAP-0007Aw-G6 for patchwork-qemu-devel@patchwork.kernel.org; Thu, 13 Dec 2018 22:29:33 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58894) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXe17-0006Bi-Dp for qemu-devel@nongnu.org; Thu, 13 Dec 2018 22:19:59 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gXe14-0007Nt-92 for qemu-devel@nongnu.org; Thu, 13 Dec 2018 22:19:56 -0500 Received: from mail-oi1-x22a.google.com ([2607:f8b0:4864:20::22a]:39889) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gXe11-000792-M7 for qemu-devel@nongnu.org; Thu, 13 Dec 2018 22:19:52 -0500 Received: by mail-oi1-x22a.google.com with SMTP id i6so3464302oia.6 for ; Thu, 13 Dec 2018 19:19:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=BAbxztkWwjj+pjyiBgJ/SLhSHcB8sxV7SOKltc0srtM=; b=WTJch88Pwh/IJ3fyx0/EqHgvRl6F9ukcKKscUqWMfD05c5ixeWEmq0ePXArAq/p9ar LdiKBNbeQPtSsfWvEvlnBbli0D8tUxinOLX7I/Kmci+Q9xX5Oeitlx+QXO4Ox79F/i1N 9Ws306Z78X6diifIO9az7+IqV7KuD8Yj4KDuU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=BAbxztkWwjj+pjyiBgJ/SLhSHcB8sxV7SOKltc0srtM=; b=a9ZXopU2Kl2wfehxYwJVcKjaBVHWcvor+Sm40Sdq7gome+/CIDTU0nq6pqupxRmn+i lDUdvToXQdLClwDKzNCdJW4U0vgl5B7h9cFHiO2ZTCaR2hWP2ra53ktwcY6RJleMPI0n q++OKBwo55GfGWSDpFnf10qNzTcnT2SEoUsbR6G/nmTT2XvPGId1/HWXM3aD1QU99Vpd e1B+mHaw3HYhcZrg2/bTF507i+31n1jq3tJVcQOKiXuwKfDFn7yi9nCCF6cYyrB6Q7uJ J4+F5VHTOODjHVzsV0zV4s5TcFWsjWGiYdEFpqWA0ENlheNE+UONa4SO2/+H2ca+a3sa ZQ4A== X-Gm-Message-State: AA+aEWYv6z/3FOKYgXmzRZzVFXdeUqo8JHCBqKDD75aTTLsrYm8lfVKK Wm5HuHJNnG4+jgcJVCf4aVavdYOjBT0BXA== X-Google-Smtp-Source: AFSGD/UrejQq/G7N7uq7uoh4PmA2B/k9jHon756V8Mi+LY0QobPTTRvm+/on7P0rMmBPTtgmXp3cUg== X-Received: by 2002:aca:4ed8:: with SMTP id c207mr857480oib.276.1544757587712; Thu, 13 Dec 2018 19:19:47 -0800 (PST) Received: from cloudburst.twiddle.net ([187.217.227.243]) by smtp.gmail.com with ESMTPSA id g138sm2367537oib.26.2018.12.13.19.19.46 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 13 Dec 2018 19:19:46 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 13 Dec 2018 21:19:10 -0600 Message-Id: <20181214031923.29527-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181214031923.29527-1-richard.henderson@linaro.org> References: <20181214031923.29527-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::22a Subject: [Qemu-devel] [PULL 19/32] tcg/i386: Implement INDEX_op_extr{lh}_i64_i32 for 32-bit guests X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP This preserves the invariant that all TCG_TYPE_I32 values are zero-extended in the 64-bit host register. Reviewed-by: Emilio G. Cota Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.h | 5 +++-- tcg/i386/tcg-target.inc.c | 6 ++++++ 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 2441658865..c523d5f5e1 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -135,8 +135,9 @@ extern bool have_avx2; #define TCG_TARGET_HAS_direct_jump 1 #if TCG_TARGET_REG_BITS == 64 -#define TCG_TARGET_HAS_extrl_i64_i32 0 -#define TCG_TARGET_HAS_extrh_i64_i32 0 +/* Keep target addresses zero-extended in a register. */ +#define TCG_TARGET_HAS_extrl_i64_i32 (TARGET_LONG_BITS == 32) +#define TCG_TARGET_HAS_extrh_i64_i32 (TARGET_LONG_BITS == 32) #define TCG_TARGET_HAS_div2_i64 1 #define TCG_TARGET_HAS_rot_i64 1 #define TCG_TARGET_HAS_ext8s_i64 1 diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 695b406b4e..fe864e9ef9 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -2549,12 +2549,16 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, break; case INDEX_op_extu_i32_i64: case INDEX_op_ext32u_i64: + case INDEX_op_extrl_i64_i32: tcg_out_ext32u(s, a0, a1); break; case INDEX_op_ext_i32_i64: case INDEX_op_ext32s_i64: tcg_out_ext32s(s, a0, a1); break; + case INDEX_op_extrh_i64_i32: + tcg_out_shifti(s, SHIFT_SHR + P_REXW, a0, 32); + break; #endif OP_32_64(deposit): @@ -2918,6 +2922,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_neg_i64: case INDEX_op_not_i32: case INDEX_op_not_i64: + case INDEX_op_extrh_i64_i32: return &r_0; case INDEX_op_ext8s_i32: @@ -2933,6 +2938,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_ext32u_i64: case INDEX_op_ext_i32_i64: case INDEX_op_extu_i32_i64: + case INDEX_op_extrl_i64_i32: case INDEX_op_extract_i32: case INDEX_op_extract_i64: case INDEX_op_sextract_i32: