From patchwork Fri Dec 21 16:03:01 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 10740675 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0325F13B5 for ; Fri, 21 Dec 2018 16:13:11 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E6B85284B9 for ; Fri, 21 Dec 2018 16:13:10 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id DB167284DA; Fri, 21 Dec 2018 16:13:10 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 70136284B9 for ; Fri, 21 Dec 2018 16:13:10 +0000 (UTC) Received: from localhost ([::1]:46466 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gaNQD-0001uI-IV for patchwork-qemu-devel@patchwork.kernel.org; Fri, 21 Dec 2018 11:13:09 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53083) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gaNHP-0001gc-Kh for qemu-devel@nongnu.org; Fri, 21 Dec 2018 11:04:04 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gaNHO-0004GL-Ct for qemu-devel@nongnu.org; Fri, 21 Dec 2018 11:04:03 -0500 Received: from mail-qk1-x741.google.com ([2607:f8b0:4864:20::741]:34492) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gaNHN-000488-Sv for qemu-devel@nongnu.org; Fri, 21 Dec 2018 11:04:02 -0500 Received: by mail-qk1-x741.google.com with SMTP id q8so3364138qke.1 for ; Fri, 21 Dec 2018 08:03:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=subject:date:message-id:in-reply-to:references:cc:from:to; bh=WHGAQUfOGf/lF2aQbiDJ1O5xra2r7l4uqRWZE5qJgIs=; b=InkDlxoMnrVROvjw+pUN7VTOQ71R3JauNHYjjqmmICSfsBbqehlloIEukaXYl+ny8v OwvArBjRSp8cVovL0BcZEUvax42DXusETr0d3OwL8nAd2SxYygByV7Zhe/NxOt+8DBz/ njtEg8tIbd3Y7XGayn6wPqctay5iqysmkNGF5jzmb6V1BVOST7XNS+GNZu/WaWH9Y4QX nwuZ+DYnzBMwl7AeW2ltdykl546dtTRCU9J6fxUlLhdni7mZewiV7OauHrqEXomwcnQ1 qj8DHAsvQgXktWkLAkapvZNbc+WzrjMPHKv2N3tUYSLJJjRK5hhYT4a4bYe6U2sLIfa9 b25A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:date:message-id:in-reply-to:references :cc:from:to; bh=WHGAQUfOGf/lF2aQbiDJ1O5xra2r7l4uqRWZE5qJgIs=; b=svmvATC2hQe0PISBL1lSADUjhRQyKhChvIvK7U6CKPN9Le07B8gOtHBP60FRiLC4S5 vi/cRuXBgTPgSbm8HC35BKhDHRYQfxBQm9sK9ASXZXwNyE7U6GwSK6XqUzPftmbnRGwu te7qbu1L8LQ8Z2F7TgNwLpZ3/I2ZR9EKq/4IaZdhMvxH7+jidz1bsxDutwhTkMJvZfSx pBGrd/4PMZSss/vdoLzmiJuAQlOCQcyWP0UAZQimOjugxCOOYCK4QcPqYSk6/WckVB4X 7pOgutEA/dC+K4WYyCXkFIJxnVwxePFZGJ3vR8ytoLmUCDOPKbHMW2EbEoxsICiXuXgA AOUw== X-Gm-Message-State: AJcUukf4SuhDPQ9xod8IUp6B+DxyEJ6rs4pgRDUgshVSwp6zqcX5NhSQ xlFYZ3jLGKCTJQ/ZjWqatsIVRez5wv8= X-Google-Smtp-Source: ALg8bN60k6U+LR28uLnJXV19pdqdkU++wxPD3t7uYu/DNCeCHIpxvTtUzgfqnb5i70pFYAGX+Jo8WQ== X-Received: by 2002:a37:a391:: with SMTP id m139mr2766254qke.11.1545408227566; Fri, 21 Dec 2018 08:03:47 -0800 (PST) Received: from localhost ([2601:182:c980:96c:8dd:4488:90b1:59d1]) by smtp.gmail.com with ESMTPSA id u45sm6110081qtk.33.2018.12.21.08.03.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 21 Dec 2018 08:03:46 -0800 (PST) Date: Fri, 21 Dec 2018 08:03:01 -0800 Message-Id: <20181221160307.14819-9-palmer@sifive.com> X-Mailer: git-send-email 2.18.1 In-Reply-To: <20181221160307.14819-1-palmer@sifive.com> References: <20181221160307.14819-1-palmer@sifive.com> From: Palmer Dabbelt To: qemu-riscv@nongnu.org X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::741 Subject: [Qemu-devel] [PULL 08/14] RISC-V: Fix CLINT timecmp low 32-bit writes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Bastian Koppelmann , Palmer Dabbelt , qemu-devel@nongnu.org, Michael Clark , Alistair Francis Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Michael Clark A missing shift made updates to the low order bits of timecmp erroneously copy the old low order bits into the high order bits of the 64-bit timecmp register. Add the missing shift and rename timecmp local variables to timecmp_hi and timecmp_lo. This bug didn't show up as the low order bits are usually written first followed by the high order bits meaning the high order bits contained an invalid value between the timecmp_lo and timecmp_hi update. Cc: Palmer Dabbelt Cc: Sagar Karandikar Cc: Bastian Koppelmann Cc: Alistair Francis Co-Authored-by: Johannes Haring Signed-off-by: Michael Clark Reviewed-by: Alistair Francis Signed-off-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- hw/riscv/sifive_clint.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/riscv/sifive_clint.c b/hw/riscv/sifive_clint.c index 0d2fd52487e6..d4c159e93736 100644 --- a/hw/riscv/sifive_clint.c +++ b/hw/riscv/sifive_clint.c @@ -146,15 +146,15 @@ static void sifive_clint_write(void *opaque, hwaddr addr, uint64_t value, error_report("clint: invalid timecmp hartid: %zu", hartid); } else if ((addr & 0x7) == 0) { /* timecmp_lo */ - uint64_t timecmp = env->timecmp; + uint64_t timecmp_hi = env->timecmp >> 32; sifive_clint_write_timecmp(RISCV_CPU(cpu), - timecmp << 32 | (value & 0xFFFFFFFF)); + timecmp_hi << 32 | (value & 0xFFFFFFFF)); return; } else if ((addr & 0x7) == 4) { /* timecmp_hi */ - uint64_t timecmp = env->timecmp; + uint64_t timecmp_lo = env->timecmp; sifive_clint_write_timecmp(RISCV_CPU(cpu), - value << 32 | (timecmp & 0xFFFFFFFF)); + value << 32 | (timecmp_lo & 0xFFFFFFFF)); } else { error_report("clint: invalid timecmp write: %08x", (uint32_t)addr); }