From patchwork Wed Dec 26 17:20:01 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 10743249 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D63E113A4 for ; Wed, 26 Dec 2018 17:28:14 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B94FD287AC for ; Wed, 26 Dec 2018 17:28:14 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id AC6B4287B1; Wed, 26 Dec 2018 17:28:14 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 3F2F2287AC for ; Wed, 26 Dec 2018 17:28:14 +0000 (UTC) Received: from localhost ([127.0.0.1]:47456 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gcCyb-0005qj-Dz for patchwork-qemu-devel@patchwork.kernel.org; Wed, 26 Dec 2018 12:28:13 -0500 Received: from eggs.gnu.org ([208.118.235.92]:47964) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gcCrL-0004Bn-E4 for qemu-devel@nongnu.org; Wed, 26 Dec 2018 12:20:44 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gcCrE-0007r1-2I for qemu-devel@nongnu.org; Wed, 26 Dec 2018 12:20:39 -0500 Received: from mail-qt1-x835.google.com ([2607:f8b0:4864:20::835]:37446) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gcCrD-0007nT-MV for qemu-devel@nongnu.org; Wed, 26 Dec 2018 12:20:35 -0500 Received: by mail-qt1-x835.google.com with SMTP id t33so17841233qtt.4 for ; Wed, 26 Dec 2018 09:20:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=subject:date:message-id:in-reply-to:references:cc:from:to; bh=B2OUXWtoyq20lymvhtwIjTpztHbwOwadgrVPRgraXAk=; b=DWfKcv8COuZdj3hME3zB0DQapvOiV4Ot+yZgaqB5bwyMMa9xY+mdGtdn0lonvj0SPo CL94u7NMTYP888e8sAj/a5pfjWJPm+DneW4JutZEA4fzUmwNzfXDThZVzyoxHcUfcKTf /tnFAzOPgMtQ5hIzx+OHme1yG4Uny2Bi6OP+VGsHZ2+wTsC9TJNi5bBnsWmlbUDlWnu0 avidV1UJuacb+2Z2Z75DY5riFXCRaTW5WejySf3fWAj8VTy7toZSfWaJar/tXx5UswTz figLZMOSg3fTN6dJWCR7BtdaJ4NOV4Z1t21DKlxAwHOWc0S1grPlTliqEq3EIC7ffn5a rH1w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:date:message-id:in-reply-to:references :cc:from:to; bh=B2OUXWtoyq20lymvhtwIjTpztHbwOwadgrVPRgraXAk=; b=sVDiGNn8w7WoP6bAQ044xCBIZ0PZVd/Hhyj//KJRj94zbXjfPIpYLvLPOygBlBEw/f sOMlc0rHPmA1Ry8zeZ4idSALsFLNIyUX/QSJfzXmfIcC3Ipc0PPQkJAlmX0ZHC08UxQt nXTQmEy+o3hk2xsNmqhfjC/0bP5y8XzjdgNrX9BOEqA6O1uNy2ZiHzqKU68xQuMvZFkt S2KdRAu7P1x0dn/zX+QbVYdSBvvwzawLp5Rs8jPcKDP8fDBSnRwmse36fANa2e8jIxSS +RFyNw9ievjIZBVwKgNpyQvMqfD6hzDbvENe1xC32EI/oE0M5XpSCwEeIZYu605M6zT4 G7Tg== X-Gm-Message-State: AJcUukeFJ7ijeXHDN4wcAUoSvp9qLc7akkuMQIlQ5AOGxH76SeUkBVjq ALuz4saWojN9xfgZYUBXQAhRsw== X-Google-Smtp-Source: ALg8bN5ZmdyePWoz0D8XP6oE7sBng7s+FVAcaHPT2eIsWMkiquSjbPIFSMcheEzmx35wiSUGMEuKbQ== X-Received: by 2002:a0c:fd8a:: with SMTP id p10mr19375827qvr.48.1545844831754; Wed, 26 Dec 2018 09:20:31 -0800 (PST) Received: from localhost ([2601:182:c980:96c:8dd:4488:90b1:59d1]) by smtp.gmail.com with ESMTPSA id r16sm19613376qkh.71.2018.12.26.09.20.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 26 Dec 2018 09:20:31 -0800 (PST) Date: Wed, 26 Dec 2018 09:20:01 -0800 Message-Id: <20181226172005.26990-11-palmer@sifive.com> X-Mailer: git-send-email 2.18.1 In-Reply-To: <20181226172005.26990-1-palmer@sifive.com> References: <20181226172005.26990-1-palmer@sifive.com> From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::835 Subject: [Qemu-devel] [PULL 10/14] RISC-V: Enable second UART on sifive_e and sifive_u X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Sagar Karandikar , Bastian Koppelmann , Palmer Dabbelt , qemu-devel@nongnu.org, Michael Clark , Alistair Francis Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Michael Clark Previously the second UARTs on the sifive_e and sifive_u machines where disabled due to check-qtest-riscv32 and check-qtest-riscv64 failures. Recent changes in the QEMU core serial code have resolved these failures so the second UARTs can be instantiated. Cc: Palmer Dabbelt Cc: Sagar Karandikar Cc: Bastian Koppelmann Cc: Alistair Francis Signed-off-by: Michael Clark Reviewed-by: Alistair Francis Signed-off-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- hw/riscv/sifive_e.c | 5 ++--- hw/riscv/sifive_u.c | 5 ++--- 2 files changed, 4 insertions(+), 6 deletions(-) diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index cb513cc3bb50..5d9d65ff29ab 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -192,9 +192,8 @@ static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp) memmap[SIFIVE_E_QSPI0].base, memmap[SIFIVE_E_QSPI0].size); sifive_mmio_emulate(sys_mem, "riscv.sifive.e.pwm0", memmap[SIFIVE_E_PWM0].base, memmap[SIFIVE_E_PWM0].size); - /* sifive_uart_create(sys_mem, memmap[SIFIVE_E_UART1].base, - serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), - SIFIVE_E_UART1_IRQ)); */ + sifive_uart_create(sys_mem, memmap[SIFIVE_E_UART1].base, + serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART1_IRQ)); sifive_mmio_emulate(sys_mem, "riscv.sifive.e.qspi1", memmap[SIFIVE_E_QSPI1].base, memmap[SIFIVE_E_QSPI1].size); sifive_mmio_emulate(sys_mem, "riscv.sifive.e.pwm1", diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 849fa2e6311a..3bd3b67507f8 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -368,9 +368,8 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp) memmap[SIFIVE_U_PLIC].size); sifive_uart_create(system_memory, memmap[SIFIVE_U_UART0].base, serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ)); - /* sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base, - serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), - SIFIVE_U_UART1_IRQ)); */ + sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base, + serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ)); sifive_clint_create(memmap[SIFIVE_U_CLINT].base, memmap[SIFIVE_U_CLINT].size, smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);