From patchwork Wed Jan 2 05:57:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 10746101 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0D6A21399 for ; Wed, 2 Jan 2019 05:59:48 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id F1B2F28856 for ; Wed, 2 Jan 2019 05:59:47 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E63692885E; Wed, 2 Jan 2019 05:59:47 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI autolearn=ham version=3.3.1 Received: from listsout.gnu.org (listsout.gnu.org [209.51.188.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 579DD28875 for ; Wed, 2 Jan 2019 05:59:47 +0000 (UTC) Received: from localhost ([127.0.0.1]:42131 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1geZZC-0004LZ-9Q for patchwork-qemu-devel@patchwork.kernel.org; Wed, 02 Jan 2019 00:59:46 -0500 Received: from eggs.gnu.org ([208.118.235.92]:48602) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1geZXh-0002hq-0r for qemu-devel@nongnu.org; Wed, 02 Jan 2019 00:58:16 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1geZXd-0005yP-Rc for qemu-devel@nongnu.org; Wed, 02 Jan 2019 00:58:12 -0500 Received: from 7.mo179.mail-out.ovh.net ([46.105.61.94]:32920) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1geZXd-0005vM-LK for qemu-devel@nongnu.org; Wed, 02 Jan 2019 00:58:09 -0500 Received: from player773.ha.ovh.net (unknown [10.109.160.143]) by mo179.mail-out.ovh.net (Postfix) with ESMTP id F3EC610D019 for ; Wed, 2 Jan 2019 06:58:01 +0100 (CET) Received: from kaod.org (lfbn-1-10605-110.w90-89.abo.wanadoo.fr [90.89.196.110]) (Authenticated sender: clg@kaod.org) by player773.ha.ovh.net (Postfix) with ESMTPSA id 0208113D1A67; Wed, 2 Jan 2019 05:57:55 +0000 (UTC) From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: David Gibson Date: Wed, 2 Jan 2019 06:57:34 +0100 Message-Id: <20190102055743.5052-2-clg@kaod.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190102055743.5052-1-clg@kaod.org> References: <20190102055743.5052-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 5974306383545404390 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedtledrudehgdeltdcutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 46.105.61.94 Subject: [Qemu-devel] [PATCH 01/10] spapr: modify the prototype of the cpu_intc_create() method X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, =?utf-8?q?C=C3=A9dric_Le_Goa?= =?utf-8?q?ter?= Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Today, the interrupt presenter is linked to a CPU using the cpu_intc_create() method of the sPAPR IRQ backend. The resulting object is assigned to the PowerPCCPU 'intc' pointer whatever the interrupt mode, XICS or XIVE. To support the 'dual' interrupt mode, we will need to distinguish between the two presenter objects and for that, we plan to introduce a second interrupt presenter object pointer under the PowerPCCPU. The modifications below move the assignment of the presenter object under the cpu_intc_create() method to prepare ground for the future changes. Both sPAPR and PowerNV machines are impacted. Signed-off-by: Cédric Le Goater --- include/hw/ppc/pnv.h | 2 +- include/hw/ppc/spapr_irq.h | 4 ++-- hw/ppc/pnv.c | 23 ++++++++++++++++------- hw/ppc/pnv_core.c | 2 +- hw/ppc/spapr_cpu_core.c | 2 +- hw/ppc/spapr_irq.c | 34 ++++++++++++++++++++++++++-------- 6 files changed, 47 insertions(+), 20 deletions(-) diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index 86d5f54e5459..6b65397b7ebf 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -98,7 +98,7 @@ typedef struct PnvChipClass { DeviceRealize parent_realize; uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id); - Object *(*intc_create)(PnvChip *chip, Object *child, Error **errp); + void (*intc_create)(PnvChip *chip, PowerPCCPU *cpu, Error **errp); ISABus *(*isa_create)(PnvChip *chip, Error **errp); } PnvChipClass; diff --git a/include/hw/ppc/spapr_irq.h b/include/hw/ppc/spapr_irq.h index b34d5a00381b..d03d4d7ce687 100644 --- a/include/hw/ppc/spapr_irq.h +++ b/include/hw/ppc/spapr_irq.h @@ -42,8 +42,8 @@ typedef struct sPAPRIrq { void (*print_info)(sPAPRMachineState *spapr, Monitor *mon); void (*dt_populate)(sPAPRMachineState *spapr, uint32_t nr_servers, void *fdt, uint32_t phandle); - Object *(*cpu_intc_create)(sPAPRMachineState *spapr, Object *cpu, - Error **errp); + void (*cpu_intc_create)(sPAPRMachineState *spapr, PowerPCCPU *cpu, + Error **errp); int (*post_load)(sPAPRMachineState *spapr, int version_id); void (*reset)(sPAPRMachineState *spapr, Error **errp); } sPAPRIrq; diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 346f5e7aedb5..8e83be54fca1 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -668,11 +668,20 @@ static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id) return (chip->chip_id << 7) | (core_id << 3); } -static Object *pnv_chip_power8_intc_create(PnvChip *chip, Object *child, - Error **errp) +static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu, + Error **errp) { - return icp_create(child, TYPE_PNV_ICP, XICS_FABRIC(qdev_get_machine()), - errp); + Error *local_err = NULL; + Object *obj; + + obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, XICS_FABRIC(qdev_get_machine()), + &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + + cpu->intc = obj; } /* @@ -690,10 +699,10 @@ static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id) return (chip->chip_id << 8) | (core_id << 2); } -static Object *pnv_chip_power9_intc_create(PnvChip *chip, Object *child, - Error **errp) +static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu, + Error **errp) { - return NULL; + return; } /* Allowed core identifiers on a POWER8 Processor Chip : diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c index ad1bcc79904f..120273774874 100644 --- a/hw/ppc/pnv_core.c +++ b/hw/ppc/pnv_core.c @@ -114,7 +114,7 @@ static void pnv_realize_vcpu(PowerPCCPU *cpu, PnvChip *chip, Error **errp) return; } - cpu->intc = pcc->intc_create(chip, OBJECT(cpu), &local_err); + pcc->intc_create(chip, cpu, &local_err); if (local_err) { error_propagate(errp, local_err); return; diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c index 82666436e9b4..2739b2a4b818 100644 --- a/hw/ppc/spapr_cpu_core.c +++ b/hw/ppc/spapr_cpu_core.c @@ -232,7 +232,7 @@ static void spapr_realize_vcpu(PowerPCCPU *cpu, sPAPRMachineState *spapr, qemu_register_reset(spapr_cpu_reset, cpu); spapr_cpu_reset(cpu); - cpu->intc = spapr->irq->cpu_intc_create(spapr, OBJECT(cpu), &local_err); + spapr->irq->cpu_intc_create(spapr, cpu, &local_err); if (local_err) { goto error_unregister; } diff --git a/hw/ppc/spapr_irq.c b/hw/ppc/spapr_irq.c index 7b3b5afec212..2d2e17b66533 100644 --- a/hw/ppc/spapr_irq.c +++ b/hw/ppc/spapr_irq.c @@ -190,10 +190,20 @@ static void spapr_irq_print_info_xics(sPAPRMachineState *spapr, Monitor *mon) ics_pic_print_info(spapr->ics, mon); } -static Object *spapr_irq_cpu_intc_create_xics(sPAPRMachineState *spapr, - Object *cpu, Error **errp) +static void spapr_irq_cpu_intc_create_xics(sPAPRMachineState *spapr, + PowerPCCPU *cpu, Error **errp) { - return icp_create(cpu, spapr->icp_type, XICS_FABRIC(spapr), errp); + Error *local_err = NULL; + Object *obj; + + obj = icp_create(OBJECT(cpu), spapr->icp_type, XICS_FABRIC(spapr), + &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + + cpu->intc = obj; } static int spapr_irq_post_load_xics(sPAPRMachineState *spapr, int version_id) @@ -301,17 +311,25 @@ static void spapr_irq_print_info_xive(sPAPRMachineState *spapr, spapr_xive_pic_print_info(spapr->xive, mon); } -static Object *spapr_irq_cpu_intc_create_xive(sPAPRMachineState *spapr, - Object *cpu, Error **errp) +static void spapr_irq_cpu_intc_create_xive(sPAPRMachineState *spapr, + PowerPCCPU *cpu, Error **errp) { - Object *obj = xive_tctx_create(cpu, XIVE_ROUTER(spapr->xive), errp); + Error *local_err = NULL; + Object *obj; + + obj = xive_tctx_create(OBJECT(cpu), XIVE_ROUTER(spapr->xive), &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + + cpu->intc = obj; /* * (TCG) Early setting the OS CAM line for hotplugged CPUs as they - * don't benificiate from the reset of the XIVE IRQ backend + * don't beneficiate from the reset of the XIVE IRQ backend */ spapr_xive_set_tctx_os_cam(XIVE_TCTX(obj)); - return obj; } static int spapr_irq_post_load_xive(sPAPRMachineState *spapr, int version_id)