Message ID | 20190107101041.765-1-eric.auger@redhat.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | [v3] hw/arm/virt-acpi-build: Set COHACC override flag in IORT SMMUv3 node | expand |
On Mon, 7 Jan 2019 at 10:10, Eric Auger <eric.auger@redhat.com> wrote: > > Let's report IO-coherent access is supported for translation > table walks, descriptor fetches and queues by setting the COHACC > override flag. Without that, we observe wrong command opcodes. > The DT description also advertises the dma coherency. > > Fixes a703b4f6c1ee ("hw/arm/virt-acpi-build: Add smmuv3 node in IORT table") > > Signed-off-by: Eric Auger <eric.auger@redhat.com> > Reported-by: Shameerali Kolothum Thodi <shameerali.kolothum.thodi@huawei.com> > Tested-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com> > Reviewed-by: Andrew Jones <drjones@redhat.com> > > --- > v2 -> v3: > - added cpu_to_le32 > --- Applied to target-arm.next, thanks. -- PMM
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 95fad6f0ce..04b62c714d 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -418,6 +418,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) smmu->mapping_count = cpu_to_le32(1); smmu->mapping_offset = cpu_to_le32(sizeof(*smmu)); smmu->base_address = cpu_to_le64(vms->memmap[VIRT_SMMU].base); + smmu->flags = cpu_to_le32(ACPI_IORT_SMMU_V3_COHACC_OVERRIDE); smmu->event_gsiv = cpu_to_le32(irq); smmu->pri_gsiv = cpu_to_le32(irq + 1); smmu->gerr_gsiv = cpu_to_le32(irq + 2); diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h index 5021cb9e79..df37f68757 100644 --- a/include/hw/acpi/acpi-defs.h +++ b/include/hw/acpi/acpi-defs.h @@ -623,6 +623,8 @@ struct AcpiIortItsGroup { } QEMU_PACKED; typedef struct AcpiIortItsGroup AcpiIortItsGroup; +#define ACPI_IORT_SMMU_V3_COHACC_OVERRIDE 1 + struct AcpiIortSmmu3 { ACPI_IORT_NODE_HEADER_DEF uint64_t base_address;