From patchwork Tue Jan 22 17:01:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabiano Rosas X-Patchwork-Id: 10776083 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CCE35746 for ; Tue, 22 Jan 2019 18:41:54 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BCB492BB9A for ; Tue, 22 Jan 2019 18:41:54 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B10EC2BB98; Tue, 22 Jan 2019 18:41:54 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 28B262BB96 for ; Tue, 22 Jan 2019 18:41:54 +0000 (UTC) Received: from localhost ([127.0.0.1]:47044 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gm0zh-0008AZ-5s for patchwork-qemu-devel@patchwork.kernel.org; Tue, 22 Jan 2019 13:41:53 -0500 Received: from eggs.gnu.org ([209.51.188.92]:38721) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gm0wF-0005FA-IM for qemu-devel@nongnu.org; Tue, 22 Jan 2019 13:38:23 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gm0w5-00005g-AL for qemu-devel@nongnu.org; Tue, 22 Jan 2019 13:38:19 -0500 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:48736) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gm0w4-0008LJ-OS for qemu-devel@nongnu.org; Tue, 22 Jan 2019 13:38:09 -0500 Received: from pps.filterd (m0098394.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x0MGwsFY070774 for ; Tue, 22 Jan 2019 12:01:23 -0500 Received: from e16.ny.us.ibm.com (e16.ny.us.ibm.com [129.33.205.206]) by mx0a-001b2d01.pphosted.com with ESMTP id 2q65xtc26u-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Tue, 22 Jan 2019 12:01:22 -0500 Received: from localhost by e16.ny.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Tue, 22 Jan 2019 17:01:18 -0000 Received: from b01ledav005.gho.pok.ibm.com (b01ledav005.gho.pok.ibm.com [9.57.199.110]) by b01cxnp22034.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x0MH1HPd12714206 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 22 Jan 2019 17:01:17 GMT Received: from b01ledav005.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id AD433AE05F; Tue, 22 Jan 2019 17:01:17 +0000 (GMT) Received: from b01ledav005.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id BDDD6AE06B; Tue, 22 Jan 2019 17:01:16 +0000 (GMT) Received: from farosas.linux.ibm.com.br.ibm.com (unknown [9.86.26.87]) by b01ledav005.gho.pok.ibm.com (Postfix) with ESMTP; Tue, 22 Jan 2019 17:01:16 +0000 (GMT) From: Fabiano Rosas To: qemu-devel@nongnu.org Date: Tue, 22 Jan 2019 15:01:10 -0200 X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190122170112.8706-1-farosas@linux.ibm.com> References: <20190122170112.8706-1-farosas@linux.ibm.com> X-TM-AS-GCONF: 00 x-cbid: 19012217-0072-0000-0000-000003EDBC46 X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00010456; HX=3.00000242; KW=3.00000007; PH=3.00000004; SC=3.00000275; SDB=6.01150216; UDB=6.00599394; IPR=6.00930548; MB=3.00025241; MTD=3.00000008; XFM=3.00000015; UTC=2019-01-22 17:01:20 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19012217-0073-0000-0000-00004AE737E8 Message-Id: <20190122170112.8706-2-farosas@linux.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-01-22_09:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=3 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1901220131 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 148.163.156.1 Subject: [Qemu-devel] [PATCH v4 1/3] target/ppc: Add SPRs XML generation code for gdbstub X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, groug@kaod.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP A following patch will add support for handling the Special Purpose Registers (SPR) in GDB via gdbstub. For that purpose, GDB needs to be provided with an XML description of the registers (see gdb-xml directory). This patch adds the code that generates the XML dynamically based on the SPRs already defined in the machine. This eliminates the need for several XML files to match each possible ppc machine. A "group" is defined so that the GDB command `info registers spr` can be used. Signed-off-by: Fabiano Rosas --- target/ppc/cpu-qom.h | 4 +++ target/ppc/cpu.h | 5 +++ target/ppc/gdbstub.c | 60 +++++++++++++++++++++++++++++++++ target/ppc/translate_init.inc.c | 4 +++ 4 files changed, 73 insertions(+) diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h index 4ea67692e2..3130802304 100644 --- a/target/ppc/cpu-qom.h +++ b/target/ppc/cpu-qom.h @@ -179,6 +179,10 @@ typedef struct PowerPCCPUClass { uint32_t flags; int bfd_mach; uint32_t l1_dcache_size, l1_icache_size; +#ifndef CONFIG_USER_ONLY + unsigned int gdb_num_sprs; + const char *gdb_spr_xml; +#endif const PPCHash64Options *hash64_opts; struct ppc_radix_page_info *radix_page_info; void (*init_proc)(CPUPPCState *env); diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index a62ff60414..850c5ba278 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -230,6 +230,7 @@ struct ppc_spr_t { void (*oea_write)(DisasContext *ctx, int spr_num, int gpr_num); void (*hea_read)(DisasContext *ctx, int gpr_num, int spr_num); void (*hea_write)(DisasContext *ctx, int spr_num, int gpr_num); + unsigned int gdb_id; #endif const char *name; target_ulong default_value; @@ -1268,6 +1269,10 @@ int ppc_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); int ppc_cpu_gdb_read_register_apple(CPUState *cpu, uint8_t *buf, int reg); int ppc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); int ppc_cpu_gdb_write_register_apple(CPUState *cpu, uint8_t *buf, int reg); +#ifndef CONFIG_USER_ONLY +void ppc_gdb_gen_spr_xml(PowerPCCPU *cpu); +const char *ppc_gdb_get_dynamic_xml(CPUState *cs, const char *xml_name); +#endif int ppc64_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, int cpuid, void *opaque); int ppc32_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, diff --git a/target/ppc/gdbstub.c b/target/ppc/gdbstub.c index 19565b584d..b2bb765506 100644 --- a/target/ppc/gdbstub.c +++ b/target/ppc/gdbstub.c @@ -319,3 +319,63 @@ int ppc_cpu_gdb_write_register_apple(CPUState *cs, uint8_t *mem_buf, int n) } return r; } + +#ifndef CONFIG_USER_ONLY +void ppc_gdb_gen_spr_xml(PowerPCCPU *cpu) +{ + PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); + CPUPPCState *env = &cpu->env; + GString *s; + unsigned int num_regs; + int i; + + if (pcc->gdb_spr_xml) { + return; + } + + s = g_string_new(NULL); + g_string_printf(s, ""); + g_string_append_printf(s, ""); + g_string_append_printf(s, ""); + + for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) { + ppc_spr_t *spr = &env->spr_cb[i]; + + if (!spr->name) { + continue; + } + + g_string_append_printf(s, "name, -1)); + g_string_append_printf(s, " bitsize=\"%d\"", TARGET_LONG_BITS); + g_string_append_printf(s, " group=\"spr\"/>"); + + /* + * GDB identifies registers based on the order they are + * presented in the XML. These ids will not match QEMU's + * representation (which follows the PowerISA). + * + * Store the position of the current register description so + * we can make the correspondence later. + */ + spr->gdb_id = num_regs; + num_regs++; + } + + g_string_append_printf(s, ""); + + pcc->gdb_num_sprs = num_regs; + pcc->gdb_spr_xml = g_string_free(s, false); +} + +const char *ppc_gdb_get_dynamic_xml(CPUState *cs, const char *xml_name) +{ + PowerPCCPU *cpu = POWERPC_CPU(cs); + PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); + + if (strcmp(xml_name, "power-spr.xml") == 0) { + return pcc->gdb_spr_xml; + } + return NULL; +} +#endif diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c index ade06cc773..710064a25d 100644 --- a/target/ppc/translate_init.inc.c +++ b/target/ppc/translate_init.inc.c @@ -8987,6 +8987,10 @@ static void init_ppc_proc(PowerPCCPU *cpu) /* PowerPC implementation specific initialisations (SPRs, timers, ...) */ (*pcc->init_proc)(env); +#if !defined(CONFIG_USER_ONLY) + ppc_gdb_gen_spr_xml(cpu); +#endif + /* MSR bits & flags consistency checks */ if (env->msr_mask & (1 << 25)) { switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {