From patchwork Mon Jan 28 09:46:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 10783495 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2AB62159A for ; Mon, 28 Jan 2019 09:55:15 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 17F802A722 for ; Mon, 28 Jan 2019 09:55:15 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 0B8902A725; Mon, 28 Jan 2019 09:55:15 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 672542A722 for ; Mon, 28 Jan 2019 09:55:14 +0000 (UTC) Received: from localhost ([127.0.0.1]:56912 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1go3dJ-0002q3-IX for patchwork-qemu-devel@patchwork.kernel.org; Mon, 28 Jan 2019 04:55:13 -0500 Received: from eggs.gnu.org ([209.51.188.92]:38340) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1go3VB-00051h-B4 for qemu-devel@nongnu.org; Mon, 28 Jan 2019 04:46:50 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1go3V9-0002lB-LR for qemu-devel@nongnu.org; Mon, 28 Jan 2019 04:46:49 -0500 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:51044) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1go3V9-0002je-Al for qemu-devel@nongnu.org; Mon, 28 Jan 2019 04:46:47 -0500 Received: from pps.filterd (m0098394.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x0S9hkg0003982 for ; Mon, 28 Jan 2019 04:46:45 -0500 Received: from e06smtp02.uk.ibm.com (e06smtp02.uk.ibm.com [195.75.94.98]) by mx0a-001b2d01.pphosted.com with ESMTP id 2q9xemjh3g-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 28 Jan 2019 04:46:45 -0500 Received: from localhost by e06smtp02.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Mon, 28 Jan 2019 09:46:40 -0000 Received: from d06av21.portsmouth.uk.ibm.com (d06av21.portsmouth.uk.ibm.com [9.149.105.232]) by b06cxnps4074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x0S9kdkZ31391912 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 28 Jan 2019 09:46:39 GMT Received: from d06av21.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 4FB825204E; Mon, 28 Jan 2019 09:46:39 +0000 (GMT) Received: from smtp.lab.toulouse-stg.fr.ibm.com (unknown [9.101.4.1]) by d06av21.portsmouth.uk.ibm.com (Postfix) with ESMTP id 20B535205A; Mon, 28 Jan 2019 09:46:39 +0000 (GMT) Received: from zorba.kaod.org.com (sig-9-145-15-166.uk.ibm.com [9.145.15.166]) by smtp.lab.toulouse-stg.fr.ibm.com (Postfix) with ESMTP id 87E5E220309; Mon, 28 Jan 2019 10:46:38 +0100 (CET) From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: David Gibson Date: Mon, 28 Jan 2019 10:46:07 +0100 X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190128094625.4428-1-clg@kaod.org> References: <20190128094625.4428-1-clg@kaod.org> MIME-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 19012809-0008-0000-0000-000002B6E36E X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19012809-0009-0000-0000-00002223210B Message-Id: <20190128094625.4428-2-clg@kaod.org> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-01-28_07:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=2 phishscore=0 bulkscore=0 spamscore=0 clxscore=1034 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1901280080 X-MIME-Autoconverted: from 8bit to quoted-printable by mx0a-001b2d01.pphosted.com id x0S9hkg0003982 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 148.163.156.1 Subject: [Qemu-devel] [PATCH 01/19] ppc/xive: hardwire the Physical CAM line of the thread context X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, =?utf-8?q?C=C3=A9dric_Le_Goa?= =?utf-8?q?ter?= Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP By default on P9, the HW CAM line (23bits) is hardwired to : 0x000||0b1||4Bit chip number||7Bit Thread number. When the block group mode is enabled at the controller level (PowerNV), the CAM line is changed for CAM compares to : 4Bit chip number||0x001||7Bit Thread number This will require changes in xive_presenter_tctx_match() possibly. This is a lowlevel functionality of the HW controller and it is not strictly needed. Leave it for later. Signed-off-by: Cédric Le Goater --- include/hw/ppc/xive.h | 1 + hw/intc/xive.c | 53 ++++++++++++++++++++++++++++++++++++++++--- hw/ppc/pnv_core.c | 16 ++++++++----- 3 files changed, 61 insertions(+), 9 deletions(-) diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h index ec3bb2aae45a..04d54e8315f7 100644 --- a/include/hw/ppc/xive.h +++ b/include/hw/ppc/xive.h @@ -319,6 +319,7 @@ typedef struct XiveTCTX { qemu_irq output; uint8_t regs[XIVE_TM_RING_COUNT * XIVE_TM_RING_SIZE]; + uint32_t hw_cam; } XiveTCTX; /* diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 2e9b8efd4342..f5642f2338de 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -469,6 +469,12 @@ static void xive_tctx_realize(DeviceState *dev, Error **errp) Object *obj; Error *local_err = NULL; + if (!tctx->hw_cam) { + error_setg(errp, "XIVE: HW CAM is not set for CPU %d", + tctx->cs->cpu_index); + return; + } + obj = object_property_get_link(OBJECT(dev), "cpu", &local_err); if (!obj) { error_propagate(errp, local_err); @@ -509,11 +515,17 @@ static const VMStateDescription vmstate_xive_tctx = { }, }; +static Property xive_tctx_properties[] = { + DEFINE_PROP_UINT32("hw-cam", XiveTCTX, hw_cam, 0), + DEFINE_PROP_END_OF_LIST(), +}; + static void xive_tctx_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); dc->desc = "XIVE Interrupt Thread Context"; + dc->props = xive_tctx_properties; dc->realize = xive_tctx_realize; dc->unrealize = xive_tctx_unrealize; dc->vmsd = &vmstate_xive_tctx; @@ -526,8 +538,21 @@ static const TypeInfo xive_tctx_info = { .class_init = xive_tctx_class_init, }; +/* + * The HW CAM line (23bits) is hardwired to : + * + * 0x000||0b1||4Bit chip number||7Bit Thread number. + */ +static uint32_t hw_cam_line(uint8_t chip_id, uint8_t tid) +{ + return 1 << 11 | (chip_id & 0xf) << 7 | (tid & 0x7f); +} + Object *xive_tctx_create(Object *cpu, XiveRouter *xrtr, Error **errp) { + CPUPPCState *env = &POWERPC_CPU(cpu)->env; + uint32_t pir = env->spr_cb[SPR_PIR].default_value; + uint32_t hw_cam = hw_cam_line((pir >> 8) & 0xf, pir & 0x7f); Error *local_err = NULL; Object *obj; @@ -535,6 +560,10 @@ Object *xive_tctx_create(Object *cpu, XiveRouter *xrtr, Error **errp) object_property_add_child(cpu, TYPE_XIVE_TCTX, obj, &error_abort); object_unref(obj); object_property_add_const_link(obj, "cpu", cpu, &error_abort); + object_property_set_int(obj, hw_cam, "hw-cam", &local_err); + if (local_err) { + goto error; + } object_property_set_bool(obj, true, "realized", &local_err); if (local_err) { goto error; @@ -1112,14 +1141,28 @@ XiveTCTX *xive_router_get_tctx(XiveRouter *xrtr, CPUState *cs) return xrc->get_tctx(xrtr, cs); } +/* + * When the block grouping is enabled, the CAM line is changed to : + * + * 4Bit chip number||0x001||7Bit Thread number. + */ +static bool xive_presenter_tctx_match_hw(XiveRouter *xrtr, XiveTCTX *tctx, + uint8_t nvt_blk, uint32_t nvt_idx) +{ + /* TODO: block group support */ + return tctx->hw_cam == hw_cam_line(nvt_blk, nvt_idx); +} + /* * The thread context register words are in big-endian format. */ -static int xive_presenter_tctx_match(XiveTCTX *tctx, uint8_t format, +static int xive_presenter_tctx_match(XiveRouter *xrtr, + XiveTCTX *tctx, uint8_t format, uint8_t nvt_blk, uint32_t nvt_idx, bool cam_ignore, uint32_t logic_serv) { uint32_t cam = xive_nvt_cam_line(nvt_blk, nvt_idx); + uint32_t qw3w2 = xive_tctx_word2(&tctx->regs[TM_QW3_HV_PHYS]); uint32_t qw2w2 = xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]); uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]); uint32_t qw0w2 = xive_tctx_word2(&tctx->regs[TM_QW0_USER]); @@ -1142,7 +1185,11 @@ static int xive_presenter_tctx_match(XiveTCTX *tctx, uint8_t format, /* F=0 & i=0: Specific NVT notification */ - /* TODO (PowerNV) : PHYS ring */ + /* PHYS ring */ + if ((be32_to_cpu(qw3w2) & TM_QW3W2_VT) && + xive_presenter_tctx_match_hw(xrtr, tctx, nvt_blk, nvt_idx)) { + return TM_QW3_HV_PHYS; + } /* HV POOL ring */ if ((be32_to_cpu(qw2w2) & TM_QW2W2_VP) && @@ -1199,7 +1246,7 @@ static bool xive_presenter_match(XiveRouter *xrtr, uint8_t format, * Check the thread context CAM lines and record matches. We * will handle CPU exception delivery later */ - ring = xive_presenter_tctx_match(tctx, format, nvt_blk, nvt_idx, + ring = xive_presenter_tctx_match(xrtr, tctx, format, nvt_blk, nvt_idx, cam_ignore, logic_serv); /* * Save the context and follow on to catch duplicates, that we diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c index 7c806da720c6..f035522b4ec9 100644 --- a/hw/ppc/pnv_core.c +++ b/hw/ppc/pnv_core.c @@ -114,12 +114,6 @@ static void pnv_realize_vcpu(PowerPCCPU *cpu, PnvChip *chip, Error **errp) return; } - pcc->intc_create(chip, cpu, &local_err); - if (local_err) { - error_propagate(errp, local_err); - return; - } - core_pir = object_property_get_uint(OBJECT(cpu), "core-pir", &error_abort); /* @@ -129,6 +123,16 @@ static void pnv_realize_vcpu(PowerPCCPU *cpu, PnvChip *chip, Error **errp) */ pir->default_value = core_pir + thread_index; + /* + * On P9, the interrupt presenter needs to hardwire the PIR value + * in the thread interrupt context of the CPU. + */ + pcc->intc_create(chip, cpu, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + /* Set time-base frequency to 512 MHz */ cpu_ppc_tb_init(env, PNV_TIMEBASE_FREQ);