From patchwork Sat Feb 2 09:43:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 10794247 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5748513B5 for ; Sat, 2 Feb 2019 09:58:01 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3A58C3154F for ; Sat, 2 Feb 2019 09:58:01 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2A34D315C6; Sat, 2 Feb 2019 09:58:01 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 81BCC3154F for ; Sat, 2 Feb 2019 09:58:00 +0000 (UTC) Received: from localhost ([127.0.0.1]:40093 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gps3j-0001LV-RI for patchwork-qemu-devel@patchwork.kernel.org; Sat, 02 Feb 2019 04:57:59 -0500 Received: from eggs.gnu.org ([209.51.188.92]:54983) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gprzI-0006zO-Ih for qemu-devel@nongnu.org; Sat, 02 Feb 2019 04:53:27 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gprq5-0005f5-UU for qemu-devel@nongnu.org; Sat, 02 Feb 2019 04:43:55 -0500 Received: from mail-ed1-x544.google.com ([2a00:1450:4864:20::544]:37760) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gprq5-0005bz-6p for qemu-devel@nongnu.org; Sat, 02 Feb 2019 04:43:53 -0500 Received: by mail-ed1-x544.google.com with SMTP id h15so7475916edb.4 for ; Sat, 02 Feb 2019 01:43:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=subject:date:message-id:in-reply-to:references:cc:from:to; bh=ihjYI8w/pHOrt/O0GHzxFvfptHP8KkD3SPdesRMFnZg=; b=UlTnc7J3KOsLni1cRH8E6TP8QgA7xdJP91jDa/GzXQ0pDYaP5Okni9usQdsB6wJ/pe h6mSJ2VbuRe0wlpvUkRjP7ciTcURo6WGPJyRZcwLQCCzhMaFuYyqych77NmcUoLYSW1y bOOcoOKzB5M0jSZwPsafEe52RUiRRKY6urEWL/gxpU3nsQWE1bac4ArdS1DweXj+Vkfb BM1dp4YDSSEa1RKrBIZRm97lxe8rP9pTeVP2O4j0n8JTC0zKYiAeunkvT0xz0xMi+P1C oj/HGYYPZaJAs9n/pPQ8KQP4tzaNl5xf2HdJyvSsbFGIIF6OADCrk1cnDV4rfpR76Gzr ZWnw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:date:message-id:in-reply-to:references :cc:from:to; bh=ihjYI8w/pHOrt/O0GHzxFvfptHP8KkD3SPdesRMFnZg=; b=ufNDSOKSxY/IcqrG9OBP+d1S8fmBqm7I9FSgPmGRsqyUzrlBGNpT10yOlRd87VtJtS 18mhwv1YIGES6Liyqek0ACpxO/bTqsAX6d0ztFp1aTm5URYz11zenIFuzXwQJljxoCnl TLro8FkQi4PxNJNGmKiWy2Xfoo8hEkkH7/LD+rIHd5YzTkrtCF6BMO5i9+7mNUnMGVyE 5TJLpV59WSoMLHlnJqTpTv5Gloqf17QN5OemRtTX2v7gcdlre6AYUDuwo2gHllsmEzmf asWSqbE13jYmBqUddwH7sCxyjaT+o7pNA6t7bXxXz6cNBwvKPsNnfRrCLkpPFkBR02+O 9XbQ== X-Gm-Message-State: AJcUukfOFlsB0wSUyc5I2qRVToNPHJobr5PDKa+fpk7QETiGvLH7uHtk 5tNrRLmX2rvqnyKF/mZuuZu7sQ== X-Google-Smtp-Source: ALg8bN66JMDLpssI6Nu3nUR09Pz5SEoV0tR5Z8kA4YG3Yhac5LRcJzugHUguieMTGMlAYBOWfipIiA== X-Received: by 2002:aa7:d749:: with SMTP id a9mr41210916eds.223.1549100629864; Sat, 02 Feb 2019 01:43:49 -0800 (PST) Received: from localhost ([2001:67c:1810:f051:fd32:55e2:f60b:183b]) by smtp.gmail.com with ESMTPSA id m14sm2793200edc.27.2019.02.02.01.43.48 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 02 Feb 2019 01:43:49 -0800 (PST) Date: Sat, 2 Feb 2019 01:43:27 -0800 Message-Id: <20190202094329.22874-9-palmer@sifive.com> X-Mailer: git-send-email 2.18.1 In-Reply-To: <20190202094329.22874-1-palmer@sifive.com> References: <20190202094329.22874-1-palmer@sifive.com> From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::544 Subject: [Qemu-devel] [PULL 08/10] RISC-V: Add misa runtime write support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Michael Clark , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Palmer Dabbelt Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Michael Clark This patch adds support for writing misa. misa is validated based on rules in the ISA specification. 'E' is mutually exclusive with all other extensions. 'D' depends on 'F' so 'D' bit is dropped if 'F' is not present. A conservative approach to consistency is taken by flushing the translation cache on misa writes. misa_mask is added to the CPU struct to store the original set of extensions. Signed-off-by: Michael Clark Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- target/riscv/cpu.c | 2 +- target/riscv/cpu.h | 4 ++- target/riscv/cpu_bits.h | 11 +++++++++ target/riscv/csr.c | 54 ++++++++++++++++++++++++++++++++++++++++- 4 files changed, 68 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 28d7e5302fb1..cc3ddc0ae4b5 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -88,7 +88,7 @@ typedef struct RISCVCPUInfo { static void set_misa(CPURISCVState *env, target_ulong misa) { - env->misa = misa; + env->misa_mask = env->misa = misa; } static void set_versions(CPURISCVState *env, int user_ver, int priv_ver) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index a97435bd7b1d..5c2aebf13251 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -86,7 +86,8 @@ so a cpu features bitfield is required, likewise for optional PMP support */ enum { RISCV_FEATURE_MMU, - RISCV_FEATURE_PMP + RISCV_FEATURE_PMP, + RISCV_FEATURE_MISA }; #define USER_VERSION_2_02_0 0x00020200 @@ -118,6 +119,7 @@ struct CPURISCVState { target_ulong user_ver; target_ulong priv_ver; target_ulong misa; + target_ulong misa_mask; uint32_t features; diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 5439f4719ee5..7afcb2468d80 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -311,10 +311,21 @@ #define MSTATUS32_SD 0x80000000 #define MSTATUS64_SD 0x8000000000000000ULL +#define MISA32_MXL 0xC0000000 +#define MISA64_MXL 0xC000000000000000ULL + +#define MXL_RV32 1 +#define MXL_RV64 2 +#define MXL_RV128 3 + #if defined(TARGET_RISCV32) #define MSTATUS_SD MSTATUS32_SD +#define MISA_MXL MISA32_MXL +#define MXL_VAL MXL_RV32 #elif defined(TARGET_RISCV64) #define MSTATUS_SD MSTATUS64_SD +#define MISA_MXL MISA64_MXL +#define MXL_VAL MXL_RV64 #endif /* sstatus CSR bits */ diff --git a/target/riscv/csr.c b/target/riscv/csr.c index e2bd374f09ed..e72fcf1265d4 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -332,6 +332,58 @@ static int read_misa(CPURISCVState *env, int csrno, target_ulong *val) return 0; } +static int write_misa(CPURISCVState *env, int csrno, target_ulong val) +{ + if (!riscv_feature(env, RISCV_FEATURE_MISA)) { + /* drop write to misa */ + return 0; + } + + /* 'I' or 'E' must be present */ + if (!(val & (RVI | RVE))) { + /* It is not, drop write to misa */ + return 0; + } + + /* 'E' excludes all other extensions */ + if (val & RVE) { + /* when we support 'E' we can do "val = RVE;" however + * for now we just drop writes if 'E' is present. + */ + return 0; + } + + /* Mask extensions that are not supported by this hart */ + val &= env->misa_mask; + + /* Mask extensions that are not supported by QEMU */ + val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU); + + /* 'D' depends on 'F', so clear 'D' if 'F' is not present */ + if ((val & RVD) && !(val & RVF)) { + val &= ~RVD; + } + + /* Suppress 'C' if next instruction is not aligned + * TODO: this should check next_pc + */ + if ((val & RVC) && (GETPC() & ~3) != 0) { + val &= ~RVC; + } + + /* misa.MXL writes are not supported by QEMU */ + val = (env->misa & MISA_MXL) | (val & ~MISA_MXL); + + /* flush translation cache */ + if (val != env->misa) { + tb_flush(CPU(riscv_env_get_cpu(env))); + } + + env->misa = val; + + return 0; +} + static int read_medeleg(CPURISCVState *env, int csrno, target_ulong *val) { *val = env->medeleg; @@ -810,7 +862,7 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { /* Machine Trap Setup */ [CSR_MSTATUS] = { any, read_mstatus, write_mstatus }, - [CSR_MISA] = { any, read_misa }, + [CSR_MISA] = { any, read_misa, write_misa }, [CSR_MIDELEG] = { any, read_mideleg, write_mideleg }, [CSR_MEDELEG] = { any, read_medeleg, write_medeleg }, [CSR_MIE] = { any, read_mie, write_mie },