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X-Received-From: 2607:f8b0:4864:20::634 Subject: [Qemu-devel] [PATCH v7 22/35] target/riscv: Remove manual decoding from gen_load() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bastian Koppelmann , Peer Adelt , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Bastian Koppelmann With decodetree we don't need to convert RISC-V opcodes into to MemOps as the old gen_load() did. Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt --- target/riscv/insn_trans/trans_rvi.inc.c | 35 +++++++++++++++---------- target/riscv/translate.c | 6 +++-- 2 files changed, 25 insertions(+), 16 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c index 000cb6a37bdd..a3e00140d7d0 100644 --- a/target/riscv/insn_trans/trans_rvi.inc.c +++ b/target/riscv/insn_trans/trans_rvi.inc.c @@ -129,34 +129,43 @@ static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a) return gen_branch(ctx, a, TCG_COND_GEU); } -static bool trans_lb(DisasContext *ctx, arg_lb *a) +static bool gen_load(DisasContext *ctx, arg_lb *a, TCGMemOp memop) { - gen_load(ctx, OPC_RISC_LB, a->rd, a->rs1, a->imm); + TCGv t0 = tcg_temp_new(); + TCGv t1 = tcg_temp_new(); + gen_get_gpr(t0, a->rs1); + tcg_gen_addi_tl(t0, t0, a->imm); + + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, memop); + gen_set_gpr(a->rd, t1); + tcg_temp_free(t0); + tcg_temp_free(t1); return true; } +static bool trans_lb(DisasContext *ctx, arg_lb *a) +{ + return gen_load(ctx, a, MO_SB); +} + static bool trans_lh(DisasContext *ctx, arg_lh *a) { - gen_load(ctx, OPC_RISC_LH, a->rd, a->rs1, a->imm); - return true; + return gen_load(ctx, a, MO_TESW); } static bool trans_lw(DisasContext *ctx, arg_lw *a) { - gen_load(ctx, OPC_RISC_LW, a->rd, a->rs1, a->imm); - return true; + return gen_load(ctx, a, MO_TESL); } static bool trans_lbu(DisasContext *ctx, arg_lbu *a) { - gen_load(ctx, OPC_RISC_LBU, a->rd, a->rs1, a->imm); - return true; + return gen_load(ctx, a, MO_UB); } static bool trans_lhu(DisasContext *ctx, arg_lhu *a) { - gen_load(ctx, OPC_RISC_LHU, a->rd, a->rs1, a->imm); - return true; + return gen_load(ctx, a, MO_TEUW); } static bool trans_sb(DisasContext *ctx, arg_sb *a) @@ -180,14 +189,12 @@ static bool trans_sw(DisasContext *ctx, arg_sw *a) #ifdef TARGET_RISCV64 static bool trans_lwu(DisasContext *ctx, arg_lwu *a) { - gen_load(ctx, OPC_RISC_LWU, a->rd, a->rs1, a->imm); - return true; + return gen_load(ctx, a, MO_TEUL); } static bool trans_ld(DisasContext *ctx, arg_ld *a) { - gen_load(ctx, OPC_RISC_LD, a->rd, a->rs1, a->imm); - return true; + return gen_load(ctx, a, MO_TEQ); } static bool trans_sd(DisasContext *ctx, arg_sd *a) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index a3e77b88f6e9..82ccb7192921 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -532,7 +532,8 @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) ctx->base.is_jmp = DISAS_NORETURN; } -static void gen_load(DisasContext *ctx, uint32_t opc, int rd, int rs1, +#ifdef TARGET_RISCV64 +static void gen_load_c(DisasContext *ctx, uint32_t opc, int rd, int rs1, target_long imm) { TCGv t0 = tcg_temp_new(); @@ -551,6 +552,7 @@ static void gen_load(DisasContext *ctx, uint32_t opc, int rd, int rs1, tcg_temp_free(t0); tcg_temp_free(t1); } +#endif static void gen_store(DisasContext *ctx, uint32_t opc, int rs1, int rs2, target_long imm) @@ -724,7 +726,7 @@ static void decode_RV32_64C0(DisasContext *ctx) case 3: #if defined(TARGET_RISCV64) /* C.LD(RV64/128) -> ld rd', offset[7:3](rs1')*/ - gen_load(ctx, OPC_RISC_LD, rd_rs2, rs1s, + gen_load_c(ctx, OPC_RISC_LD, rd_rs2, rs1s, GET_C_LD_IMM(ctx->opcode)); #else /* C.FLW (RV32) -> flw rd', offset[6:2](rs1')*/