[v7,30/35] target/riscv: Remove decode_RV32_64G()

Message ID	20190213155414.22285-31-palmer@sifive.com (mailing list archive)
State	New, archived
Headers	show Return-Path: <qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org> Date: Wed, 13 Feb 2019 07:54:09 -0800 Message-Id: <20190213155414.22285-31-palmer@sifive.com> In-Reply-To: <20190213155414.22285-1-palmer@sifive.com> References: <20190213155414.22285-1-palmer@sifive.com> From: Palmer Dabbelt <palmer@sifive.com> To: qemu-riscv@nongnu.org Subject: [Qemu-devel] [PATCH v7 30/35] target/riscv: Remove decode_RV32_64G() Precedence: list Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>, Peer Adelt <peer.adelt@hni.uni-paderborn.de>, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org>
Series	target/riscv: Convert to decodetree \| expand [v7,00/35] target/riscv: Convert to decodetree [v7,01/35] target/riscv: Move CPURISCVState pointer to DisasContext [v7,02/35] target/riscv: Activate decodetree and implemnt LUI & AUIPC [v7,03/35] target/riscv: Convert RVXI branch insns to decodetree [v7,04/35] target/riscv: Convert RV32I load/store insns to decodetree [v7,05/35] target/riscv: Convert RV64I load/store insns to decodetree [v7,06/35] target/riscv: Convert RVXI arithmetic insns to decodetree [v7,07/35] target/riscv: Convert RVXI fence insns to decodetree [v7,08/35] target/riscv: Convert RVXI csr insns to decodetree [v7,09/35] target/riscv: Convert RVXM insns to decodetree [v7,10/35] target/riscv: Convert RV32A insns to decodetree [v7,11/35] target/riscv: Convert RV64A insns to decodetree [v7,12/35] target/riscv: Convert RV32F insns to decodetree [v7,13/35] target/riscv: Convert RV64F insns to decodetree [v7,14/35] target/riscv: Convert RV32D insns to decodetree [v7,15/35] target/riscv: Convert RV64D insns to decodetree [v7,16/35] target/riscv: Convert RV priv insns to decodetree [v7,17/35] target/riscv: Convert quadrant 0 of RVXC insns to decodetree [v7,18/35] target/riscv: Convert quadrant 1 of RVXC insns to decodetree [v7,19/35] target/riscv: Convert quadrant 2 of RVXC insns to decodetree [v7,20/35] target/riscv: Remove gen_jalr() [v7,21/35] target/riscv: Remove manual decoding from gen_branch() [v7,22/35] target/riscv: Remove manual decoding from gen_load() [v7,23/35] target/riscv: Remove manual decoding from gen_store() [v7,24/35] target/riscv: Move gen_arith_imm() decoding into trans_* functions [v7,25/35] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists [v7,26/35] target/riscv: Remove shift and slt insn manual decoding [v7,27/35] target/riscv: Remove manual decoding of RV32/64M insn [v7,28/35] target/riscv: Rename trans_arith to gen_arith [v7,29/35] target/riscv: Remove gen_system() [v7,30/35] target/riscv: Remove decode_RV32_64G() [v7,31/35] target/riscv: Convert @cs_2 insns to share translation functions [v7,32/35] target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns [v7,33/35] target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64 [v7,34/35] target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64 [v7,35/35] target/riscv: Remaining rvc insn reuse 32 bit translators

Message ID

20190213155414.22285-31-palmer@sifive.com (mailing list archive)

State

New, archived

Headers

Date: Wed, 13 Feb 2019 07:54:09 -0800
Message-Id: <20190213155414.22285-31-palmer@sifive.com>
In-Reply-To: <20190213155414.22285-1-palmer@sifive.com>
References: <20190213155414.22285-1-palmer@sifive.com>
From: Palmer Dabbelt <palmer@sifive.com>
To: qemu-riscv@nongnu.org
Subject: [Qemu-devel] [PATCH v7 30/35] target/riscv: Remove decode_RV32_64G()
Precedence: list
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
	Peer Adelt <peer.adelt@hni.uni-paderborn.de>, qemu-devel@nongnu.org
Errors-To: 
 qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org
Sender: "Qemu-devel"
	<qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org>

Series

target/riscv: Convert to decodetree | expand

Commit Message

Palmer Dabbelt Feb. 13, 2019, 3:54 p.m. UTC

From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>

decodetree handles all instructions now so the fallback is not necessary
anymore.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
 target/riscv/translate.c | 21 +--------------------
 1 file changed, 1 insertion(+), 20 deletions(-)

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 65bedc966497..59c297915158 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -646,24 +646,6 @@  bool decode_insn16(DisasContext *ctx, uint16_t insn);
 #include "decode_insn16.inc.c"
 #include "insn_trans/trans_rvc.inc.c"
 
-static void decode_RV32_64G(DisasContext *ctx)
-{
-    uint32_t op;
-
-    /* We do not do misaligned address check here: the address should never be
-     * misaligned at this point. Instructions that set PC must do the check,
-     * since epc must be the address of the instruction that caused us to
-     * perform the misaligned instruction fetch */
-
-    op = MASK_OP_MAJOR(ctx->opcode);
-
-    switch (op) {
-    default:
-        gen_exception_illegal(ctx);
-        break;
-    }
-}
-
 static void decode_opc(DisasContext *ctx)
 {
     /* check for compressed insn */
@@ -680,8 +662,7 @@  static void decode_opc(DisasContext *ctx)
     } else {
         ctx->pc_succ_insn = ctx->base.pc_next + 4;
         if (!decode_insn32(ctx, ctx->opcode)) {
-            /* fallback to old decoder */
-            decode_RV32_64G(ctx);
+            gen_exception_illegal(ctx);
         }
     }
 }

[v7,30/35] target/riscv: Remove decode_RV32_64G()

Commit Message

Patch