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(jcmvbkbc-1-pt.tunnel.tserv24.sto1.ipv6.he.net. [2001:470:27:1fa::2]) by smtp.gmail.com with ESMTPSA id f16-v6sm4235745lji.88.2019.02.18.22.12.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 18 Feb 2019 22:12:41 -0800 (PST) From: Max Filippov To: qemu-devel@nongnu.org Date: Mon, 18 Feb 2019 22:11:11 -0800 Message-Id: <20190219061111.10231-24-jcmvbkbc@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190219061111.10231-1-jcmvbkbc@gmail.com> References: <20190219061111.10231-1-jcmvbkbc@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::242 Subject: [Qemu-devel] [PATCH 23/23] tests/tcg/xtensa: add FPU2000 coprocessor tests X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Max Filippov Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Max Filippov --- tests/tcg/xtensa/Makefile | 1 + tests/tcg/xtensa/test_fp_cpenable.S | 27 +++++++++++++++++++++++++++ 2 files changed, 28 insertions(+) create mode 100644 tests/tcg/xtensa/test_fp_cpenable.S diff --git a/tests/tcg/xtensa/Makefile b/tests/tcg/xtensa/Makefile index 2b323adb8d46..2bd4491769d1 100644 --- a/tests/tcg/xtensa/Makefile +++ b/tests/tcg/xtensa/Makefile @@ -42,6 +42,7 @@ TESTCASES += test_flix.tst TESTCASES += test_fp0_arith.tst TESTCASES += test_fp0_conv.tst TESTCASES += test_fp1.tst +TESTCASES += test_fp_cpenable.tst TESTCASES += test_interrupt.tst TESTCASES += test_loop.tst TESTCASES += test_lsc.tst diff --git a/tests/tcg/xtensa/test_fp_cpenable.S b/tests/tcg/xtensa/test_fp_cpenable.S new file mode 100644 index 000000000000..882bb2f3ceb1 --- /dev/null +++ b/tests/tcg/xtensa/test_fp_cpenable.S @@ -0,0 +1,27 @@ +#include "macros.inc" + +test_suite fp_cpenable + +#if XCHAL_HAVE_FP + +test rur + set_vector kernel, 2f + movi a2, 0 + wsr a2, cpenable + isync +1: + rur a2, fsr + //wfr f0, a2 + test_fail +2: + movi a2, 1b + rsr a3, epc1 + assert eq, a2, a3 + movi a2, 32 + rsr a3, exccause + assert eq, a2, a3 +test_end + +#endif + +test_suite_end