[v8,12/34] target/riscv: Convert RV64F insns to decodetree

Message ID	20190222141024.22217-13-kbastian@mail.uni-paderborn.de (mailing list archive)
State	New, archived
Headers	show Return-Path: <qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org> From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> To: sagark@eecs.berkeley.edu, palmer@sifive.com, kbastian@mail.uni-paderborn.de Date: Fri, 22 Feb 2019 15:10:02 +0100 Message-Id: <20190222141024.22217-13-kbastian@mail.uni-paderborn.de> In-Reply-To: <20190222141024.22217-1-kbastian@mail.uni-paderborn.de> References: <20190222141024.22217-1-kbastian@mail.uni-paderborn.de> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Antispam-Engine: 2.7.2.2107409, Antispam-Data: 2019.2.22.140315, AntiVirus-Engine: 5.58.0, AntiVirus-Data: 2019.2.22.5580002 Subject: [Qemu-devel] [PATCH v8 12/34] target/riscv: Convert RV64F insns to decodetree Precedence: list Cc: qemu-riscv@nongnu.org, Alistair Francis <alistair.francis@wdc.com>, peer.adelt@hni.uni-paderborn.de, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org>
Series	target/riscv: Convert to decodetree \| expand [v8,00/34] target/riscv: Convert to decodetree [v8,01/34] target/riscv: Activate decodetree and implemnt LUI & AUIPC [v8,02/34] target/riscv: Convert RVXI branch insns to decodetree [v8,03/34] target/riscv: Convert RV32I load/store insns to decodetree [v8,04/34] target/riscv: Convert RV64I load/store insns to decodetree [v8,05/34] target/riscv: Convert RVXI arithmetic insns to decodetree [v8,06/34] target/riscv: Convert RVXI fence insns to decodetree [v8,07/34] target/riscv: Convert RVXI csr insns to decodetree [v8,08/34] target/riscv: Convert RVXM insns to decodetree [v8,09/34] target/riscv: Convert RV32A insns to decodetree [v8,10/34] target/riscv: Convert RV64A insns to decodetree [v8,11/34] target/riscv: Convert RV32F insns to decodetree [v8,12/34] target/riscv: Convert RV64F insns to decodetree [v8,13/34] target/riscv: Convert RV32D insns to decodetree [v8,14/34] target/riscv: Convert RV64D insns to decodetree [v8,15/34] target/riscv: Convert RV priv insns to decodetree [v8,16/34] target/riscv: Convert quadrant 0 of RVXC insns to decodetree [v8,17/34] target/riscv: Convert quadrant 1 of RVXC insns to decodetree [v8,18/34] target/riscv: Convert quadrant 2 of RVXC insns to decodetree [v8,19/34] target/riscv: Remove gen_jalr() [v8,20/34] target/riscv: Remove manual decoding from gen_branch() [v8,21/34] target/riscv: Remove manual decoding from gen_load() [v8,22/34] target/riscv: Remove manual decoding from gen_store() [v8,23/34] target/riscv: Move gen_arith_imm() decoding into trans_* functions [v8,24/34] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists [v8,25/34] target/riscv: Remove shift and slt insn manual decoding [v8,26/34] target/riscv: Remove manual decoding of RV32/64M insn [v8,27/34] target/riscv: Rename trans_arith to gen_arith [v8,28/34] target/riscv: Remove gen_system() [v8,29/34] target/riscv: Remove decode_RV32_64G() [v8,30/34] target/riscv: Convert @cs_2 insns to share translation functions [v8,31/34] target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns [v8,32/34] target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64 [v8,33/34] target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64 [v8,34/34] target/riscv: Remaining rvc insn reuse 32 bit translators

Message ID

20190222141024.22217-13-kbastian@mail.uni-paderborn.de (mailing list archive)

State

New, archived

Headers

From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
To: sagark@eecs.berkeley.edu, palmer@sifive.com,
 kbastian@mail.uni-paderborn.de
Date: Fri, 22 Feb 2019 15:10:02 +0100
Message-Id: <20190222141024.22217-13-kbastian@mail.uni-paderborn.de>
In-Reply-To: <20190222141024.22217-1-kbastian@mail.uni-paderborn.de>
References: <20190222141024.22217-1-kbastian@mail.uni-paderborn.de>
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
Subject: [Qemu-devel] [PATCH v8 12/34] target/riscv: Convert RV64F insns to
 decodetree
Precedence: list
Cc: qemu-riscv@nongnu.org, Alistair Francis <alistair.francis@wdc.com>,
	peer.adelt@hni.uni-paderborn.de, richard.henderson@linaro.org,
	qemu-devel@nongnu.org
Errors-To: 
 qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org
Sender: "Qemu-devel"
	<qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org>

Series

target/riscv: Convert to decodetree | expand

Commit Message

Bastian Koppelmann Feb. 22, 2019, 2:10 p.m. UTC

Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
v7 -> v8:
    - add missing RVF checks

 target/riscv/insn32-64.decode           |  6 +++
 target/riscv/insn_trans/trans_rvf.inc.c | 60 +++++++++++++++++++++++++
 2 files changed, 66 insertions(+)

diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index 0bee95c984..6319f872ac 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -56,3 +56,9 @@  amomin_d   10000 . . ..... ..... 011 ..... 0101111 @atom_st
 amomax_d   10100 . . ..... ..... 011 ..... 0101111 @atom_st
 amominu_d  11000 . . ..... ..... 011 ..... 0101111 @atom_st
 amomaxu_d  11100 . . ..... ..... 011 ..... 0101111 @atom_st
+
+# *** RV64F Standard Extension (in addition to RV32F) ***
+fcvt_l_s   1100000  00010 ..... ... ..... 1010011 @r2_rm
+fcvt_lu_s  1100000  00011 ..... ... ..... 1010011 @r2_rm
+fcvt_s_l   1101000  00010 ..... ... ..... 1010011 @r2_rm
+fcvt_s_lu  1101000  00011 ..... ... ..... 1010011 @r2_rm
diff --git a/target/riscv/insn_trans/trans_rvf.inc.c b/target/riscv/insn_trans/trans_rvf.inc.c
index 0f83790349..172dbfa919 100644
--- a/target/riscv/insn_trans/trans_rvf.inc.c
+++ b/target/riscv/insn_trans/trans_rvf.inc.c
@@ -377,3 +377,63 @@  static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_w_x *a)
 
     return true;
 }
+
+#ifdef TARGET_RISCV64
+static bool trans_fcvt_l_s(DisasContext *ctx, arg_fcvt_l_s *a)
+{
+    REQUIRE_FPU;
+    REQUIRE_EXT(ctx, RVF);
+
+    TCGv t0 = tcg_temp_new();
+    gen_set_rm(ctx, a->rm);
+    gen_helper_fcvt_l_s(t0, cpu_env, cpu_fpr[a->rs1]);
+    gen_set_gpr(a->rd, t0);
+    tcg_temp_free(t0);
+    return true;
+}
+
+static bool trans_fcvt_lu_s(DisasContext *ctx, arg_fcvt_lu_s *a)
+{
+    REQUIRE_FPU;
+    REQUIRE_EXT(ctx, RVF);
+
+    TCGv t0 = tcg_temp_new();
+    gen_set_rm(ctx, a->rm);
+    gen_helper_fcvt_lu_s(t0, cpu_env, cpu_fpr[a->rs1]);
+    gen_set_gpr(a->rd, t0);
+    tcg_temp_free(t0);
+    return true;
+}
+
+static bool trans_fcvt_s_l(DisasContext *ctx, arg_fcvt_s_l *a)
+{
+    REQUIRE_FPU;
+    REQUIRE_EXT(ctx, RVF);
+
+    TCGv t0 = tcg_temp_new();
+    gen_get_gpr(t0, a->rs1);
+
+    gen_set_rm(ctx, a->rm);
+    gen_helper_fcvt_s_l(cpu_fpr[a->rd], cpu_env, t0);
+
+    mark_fs_dirty(ctx);
+    tcg_temp_free(t0);
+    return true;
+}
+
+static bool trans_fcvt_s_lu(DisasContext *ctx, arg_fcvt_s_lu *a)
+{
+    REQUIRE_FPU;
+    REQUIRE_EXT(ctx, RVF);
+
+    TCGv t0 = tcg_temp_new();
+    gen_get_gpr(t0, a->rs1);
+
+    gen_set_rm(ctx, a->rm);
+    gen_helper_fcvt_s_lu(cpu_fpr[a->rd], cpu_env, t0);
+
+    mark_fs_dirty(ctx);
+    tcg_temp_free(t0);
+    return true;
+}
+#endif

[v8,12/34] target/riscv: Convert RV64F insns to decodetree

Commit Message

Patch