[v8,19/34] target/riscv: Remove gen_jalr()

Message ID	20190222141024.22217-20-kbastian@mail.uni-paderborn.de (mailing list archive)
State	New, archived
Headers	show Return-Path: <qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org> From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> To: sagark@eecs.berkeley.edu, palmer@sifive.com, kbastian@mail.uni-paderborn.de Date: Fri, 22 Feb 2019 15:10:09 +0100 Message-Id: <20190222141024.22217-20-kbastian@mail.uni-paderborn.de> In-Reply-To: <20190222141024.22217-1-kbastian@mail.uni-paderborn.de> References: <20190222141024.22217-1-kbastian@mail.uni-paderborn.de> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Antispam-Engine: 2.7.2.2107409, Antispam-Data: 2019.2.22.140315, AntiVirus-Engine: 5.58.0, AntiVirus-Data: 2019.2.19.5580002 Subject: [Qemu-devel] [PATCH v8 19/34] target/riscv: Remove gen_jalr() Precedence: list Cc: qemu-riscv@nongnu.org, Alistair Francis <alistair.francis@wdc.com>, peer.adelt@hni.uni-paderborn.de, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org>
Series	target/riscv: Convert to decodetree \| expand [v8,00/34] target/riscv: Convert to decodetree [v8,01/34] target/riscv: Activate decodetree and implemnt LUI & AUIPC [v8,02/34] target/riscv: Convert RVXI branch insns to decodetree [v8,03/34] target/riscv: Convert RV32I load/store insns to decodetree [v8,04/34] target/riscv: Convert RV64I load/store insns to decodetree [v8,05/34] target/riscv: Convert RVXI arithmetic insns to decodetree [v8,06/34] target/riscv: Convert RVXI fence insns to decodetree [v8,07/34] target/riscv: Convert RVXI csr insns to decodetree [v8,08/34] target/riscv: Convert RVXM insns to decodetree [v8,09/34] target/riscv: Convert RV32A insns to decodetree [v8,10/34] target/riscv: Convert RV64A insns to decodetree [v8,11/34] target/riscv: Convert RV32F insns to decodetree [v8,12/34] target/riscv: Convert RV64F insns to decodetree [v8,13/34] target/riscv: Convert RV32D insns to decodetree [v8,14/34] target/riscv: Convert RV64D insns to decodetree [v8,15/34] target/riscv: Convert RV priv insns to decodetree [v8,16/34] target/riscv: Convert quadrant 0 of RVXC insns to decodetree [v8,17/34] target/riscv: Convert quadrant 1 of RVXC insns to decodetree [v8,18/34] target/riscv: Convert quadrant 2 of RVXC insns to decodetree [v8,19/34] target/riscv: Remove gen_jalr() [v8,20/34] target/riscv: Remove manual decoding from gen_branch() [v8,21/34] target/riscv: Remove manual decoding from gen_load() [v8,22/34] target/riscv: Remove manual decoding from gen_store() [v8,23/34] target/riscv: Move gen_arith_imm() decoding into trans_* functions [v8,24/34] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists [v8,25/34] target/riscv: Remove shift and slt insn manual decoding [v8,26/34] target/riscv: Remove manual decoding of RV32/64M insn [v8,27/34] target/riscv: Rename trans_arith to gen_arith [v8,28/34] target/riscv: Remove gen_system() [v8,29/34] target/riscv: Remove decode_RV32_64G() [v8,30/34] target/riscv: Convert @cs_2 insns to share translation functions [v8,31/34] target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns [v8,32/34] target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64 [v8,33/34] target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64 [v8,34/34] target/riscv: Remaining rvc insn reuse 32 bit translators

Message ID

20190222141024.22217-20-kbastian@mail.uni-paderborn.de (mailing list archive)

State

New, archived

Headers

From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
To: sagark@eecs.berkeley.edu, palmer@sifive.com,
 kbastian@mail.uni-paderborn.de
Date: Fri, 22 Feb 2019 15:10:09 +0100
Message-Id: <20190222141024.22217-20-kbastian@mail.uni-paderborn.de>
In-Reply-To: <20190222141024.22217-1-kbastian@mail.uni-paderborn.de>
References: <20190222141024.22217-1-kbastian@mail.uni-paderborn.de>
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
Subject: [Qemu-devel] [PATCH v8 19/34] target/riscv: Remove gen_jalr()
Precedence: list
Cc: qemu-riscv@nongnu.org, Alistair Francis <alistair.francis@wdc.com>,
	peer.adelt@hni.uni-paderborn.de, richard.henderson@linaro.org,
	qemu-devel@nongnu.org
Errors-To: 
 qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org
Sender: "Qemu-devel"
	<qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org>

Series

target/riscv: Convert to decodetree | expand

Commit Message

Bastian Koppelmann Feb. 22, 2019, 2:10 p.m. UTC

trans_jalr() is the only caller, so move the code into trans_jalr().

Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
v7 -> v8:
    - riscv_has_ext -> has_ext

 target/riscv/insn_trans/trans_rvi.inc.c | 28 +++++++++++++++++-
 target/riscv/translate.c                | 38 -------------------------
 2 files changed, 27 insertions(+), 39 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c
index 4a23372cb8..631a88906b 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -42,7 +42,33 @@  static bool trans_jal(DisasContext *ctx, arg_jal *a)
 
 static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
 {
-    gen_jalr(ctx, OPC_RISC_JALR, a->rd, a->rs1, a->imm);
+    /* no chaining with JALR */
+    TCGLabel *misaligned = NULL;
+    TCGv t0 = tcg_temp_new();
+
+
+    gen_get_gpr(cpu_pc, a->rs1);
+    tcg_gen_addi_tl(cpu_pc, cpu_pc, a->imm);
+    tcg_gen_andi_tl(cpu_pc, cpu_pc, (target_ulong)-2);
+
+    if (!has_ext(ctx, RVC)) {
+        misaligned = gen_new_label();
+        tcg_gen_andi_tl(t0, cpu_pc, 0x2);
+        tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0x0, misaligned);
+    }
+
+    if (a->rd != 0) {
+        tcg_gen_movi_tl(cpu_gpr[a->rd], ctx->pc_succ_insn);
+    }
+    tcg_gen_lookup_and_goto_ptr();
+
+    if (misaligned) {
+        gen_set_label(misaligned);
+        gen_exception_inst_addr_mis(ctx);
+    }
+    ctx->base.is_jmp = DISAS_NORETURN;
+
+    tcg_temp_free(t0);
     return true;
 }
 
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 80afa2c1e6..9dee2ec242 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -531,44 +531,6 @@  static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
     ctx->base.is_jmp = DISAS_NORETURN;
 }
 
-static void gen_jalr(DisasContext *ctx, uint32_t opc, int rd, int rs1,
-                     target_long imm)
-{
-    /* no chaining with JALR */
-    TCGLabel *misaligned = NULL;
-    TCGv t0 = tcg_temp_new();
-
-    switch (opc) {
-    case OPC_RISC_JALR:
-        gen_get_gpr(cpu_pc, rs1);
-        tcg_gen_addi_tl(cpu_pc, cpu_pc, imm);
-        tcg_gen_andi_tl(cpu_pc, cpu_pc, (target_ulong)-2);
-
-        if (!has_ext(ctx, RVC)) {
-            misaligned = gen_new_label();
-            tcg_gen_andi_tl(t0, cpu_pc, 0x2);
-            tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0x0, misaligned);
-        }
-
-        if (rd != 0) {
-            tcg_gen_movi_tl(cpu_gpr[rd], ctx->pc_succ_insn);
-        }
-        tcg_gen_lookup_and_goto_ptr();
-
-        if (misaligned) {
-            gen_set_label(misaligned);
-            gen_exception_inst_addr_mis(ctx);
-        }
-        ctx->base.is_jmp = DISAS_NORETURN;
-        break;
-
-    default:
-        gen_exception_illegal(ctx);
-        break;
-    }
-    tcg_temp_free(t0);
-}
-
 static void gen_branch(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
                        target_long bimm)
 {

[v8,19/34] target/riscv: Remove gen_jalr()

Commit Message

Patch