[v8,28/34] target/riscv: Remove gen_system()

Message ID	20190222141024.22217-29-kbastian@mail.uni-paderborn.de (mailing list archive)
State	New, archived
Headers	show Return-Path: <qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org> From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> To: sagark@eecs.berkeley.edu, palmer@sifive.com, kbastian@mail.uni-paderborn.de Date: Fri, 22 Feb 2019 15:10:18 +0100 Message-Id: <20190222141024.22217-29-kbastian@mail.uni-paderborn.de> In-Reply-To: <20190222141024.22217-1-kbastian@mail.uni-paderborn.de> References: <20190222141024.22217-1-kbastian@mail.uni-paderborn.de> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Antispam-Engine: 2.7.2.2107409, Antispam-Data: 2019.2.22.140616, AntiVirus-Engine: 5.58.0, AntiVirus-Data: 2019.2.19.5580002 Subject: [Qemu-devel] [PATCH v8 28/34] target/riscv: Remove gen_system() Precedence: list Cc: qemu-riscv@nongnu.org, peer.adelt@hni.uni-paderborn.de, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org>
Series	target/riscv: Convert to decodetree \| expand [v8,00/34] target/riscv: Convert to decodetree [v8,01/34] target/riscv: Activate decodetree and implemnt LUI & AUIPC [v8,02/34] target/riscv: Convert RVXI branch insns to decodetree [v8,03/34] target/riscv: Convert RV32I load/store insns to decodetree [v8,04/34] target/riscv: Convert RV64I load/store insns to decodetree [v8,05/34] target/riscv: Convert RVXI arithmetic insns to decodetree [v8,06/34] target/riscv: Convert RVXI fence insns to decodetree [v8,07/34] target/riscv: Convert RVXI csr insns to decodetree [v8,08/34] target/riscv: Convert RVXM insns to decodetree [v8,09/34] target/riscv: Convert RV32A insns to decodetree [v8,10/34] target/riscv: Convert RV64A insns to decodetree [v8,11/34] target/riscv: Convert RV32F insns to decodetree [v8,12/34] target/riscv: Convert RV64F insns to decodetree [v8,13/34] target/riscv: Convert RV32D insns to decodetree [v8,14/34] target/riscv: Convert RV64D insns to decodetree [v8,15/34] target/riscv: Convert RV priv insns to decodetree [v8,16/34] target/riscv: Convert quadrant 0 of RVXC insns to decodetree [v8,17/34] target/riscv: Convert quadrant 1 of RVXC insns to decodetree [v8,18/34] target/riscv: Convert quadrant 2 of RVXC insns to decodetree [v8,19/34] target/riscv: Remove gen_jalr() [v8,20/34] target/riscv: Remove manual decoding from gen_branch() [v8,21/34] target/riscv: Remove manual decoding from gen_load() [v8,22/34] target/riscv: Remove manual decoding from gen_store() [v8,23/34] target/riscv: Move gen_arith_imm() decoding into trans_* functions [v8,24/34] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists [v8,25/34] target/riscv: Remove shift and slt insn manual decoding [v8,26/34] target/riscv: Remove manual decoding of RV32/64M insn [v8,27/34] target/riscv: Rename trans_arith to gen_arith [v8,28/34] target/riscv: Remove gen_system() [v8,29/34] target/riscv: Remove decode_RV32_64G() [v8,30/34] target/riscv: Convert @cs_2 insns to share translation functions [v8,31/34] target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns [v8,32/34] target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64 [v8,33/34] target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64 [v8,34/34] target/riscv: Remaining rvc insn reuse 32 bit translators

Message ID

20190222141024.22217-29-kbastian@mail.uni-paderborn.de (mailing list archive)

State

New, archived

Headers

From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
To: sagark@eecs.berkeley.edu, palmer@sifive.com,
 kbastian@mail.uni-paderborn.de
Date: Fri, 22 Feb 2019 15:10:18 +0100
Message-Id: <20190222141024.22217-29-kbastian@mail.uni-paderborn.de>
In-Reply-To: <20190222141024.22217-1-kbastian@mail.uni-paderborn.de>
References: <20190222141024.22217-1-kbastian@mail.uni-paderborn.de>
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
Subject: [Qemu-devel] [PATCH v8 28/34] target/riscv: Remove gen_system()
Precedence: list
Cc: qemu-riscv@nongnu.org, peer.adelt@hni.uni-paderborn.de,
	richard.henderson@linaro.org, qemu-devel@nongnu.org
Errors-To: 
 qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org
Sender: "Qemu-devel"
	<qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org>

Series

target/riscv: Convert to decodetree | expand

Commit Message

Bastian Koppelmann Feb. 22, 2019, 2:10 p.m. UTC

with all 16 bit insns moved to decodetree no path is falling back to
gen_system(), so we can remove it.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
 target/riscv/translate.c | 34 ----------------------------------
 1 file changed, 34 deletions(-)

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index dedf4189d5..92be090bc7 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -473,33 +473,6 @@  static void gen_set_rm(DisasContext *ctx, int rm)
     tcg_temp_free_i32(t0);
 }
 
-static void gen_system(DisasContext *ctx, uint32_t opc, int rd, int rs1,
-                       int csr)
-{
-    tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
-
-    switch (opc) {
-    case OPC_RISC_ECALL:
-        switch (csr) {
-        case 0x0: /* ECALL */
-            /* always generates U-level ECALL, fixed in do_interrupt handler */
-            generate_exception(ctx, RISCV_EXCP_U_ECALL);
-            tcg_gen_exit_tb(NULL, 0); /* no chaining */
-            ctx->base.is_jmp = DISAS_NORETURN;
-            break;
-        case 0x1: /* EBREAK */
-            generate_exception(ctx, RISCV_EXCP_BREAKPOINT);
-            tcg_gen_exit_tb(NULL, 0); /* no chaining */
-            ctx->base.is_jmp = DISAS_NORETURN;
-            break;
-        default:
-            gen_exception_illegal(ctx);
-            break;
-        }
-        break;
-    }
-}
-
 static void decode_RV32_64C0(DisasContext *ctx)
 {
     uint8_t funct3 = extract32(ctx->opcode, 13, 3);
@@ -680,7 +653,6 @@  bool decode_insn16(DisasContext *ctx, uint16_t insn);
 
 static void decode_RV32_64G(DisasContext *ctx)
 {
-    int rs1, rd;
     uint32_t op;
 
     /* We do not do misaligned address check here: the address should never be
@@ -689,14 +661,8 @@  static void decode_RV32_64G(DisasContext *ctx)
      * perform the misaligned instruction fetch */
 
     op = MASK_OP_MAJOR(ctx->opcode);
-    rs1 = GET_RS1(ctx->opcode);
-    rd = GET_RD(ctx->opcode);
 
     switch (op) {
-    case OPC_RISC_SYSTEM:
-        gen_system(ctx, MASK_OP_SYSTEM(ctx->opcode), rd, rs1,
-                   (ctx->opcode & 0xFFF00000) >> 20);
-        break;
     default:
         gen_exception_illegal(ctx);
         break;

[v8,28/34] target/riscv: Remove gen_system()

Commit Message

Patch