From patchwork Wed Mar 6 08:50:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 10840683 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E4A121669 for ; Wed, 6 Mar 2019 09:17:17 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CBAC32D4DA for ; Wed, 6 Mar 2019 09:17:17 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C01D32D4E3; Wed, 6 Mar 2019 09:17:17 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id A748D2D4DA for ; Wed, 6 Mar 2019 09:17:16 +0000 (UTC) Received: from localhost ([127.0.0.1]:56767 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h1SWm-0002UE-QD for patchwork-qemu-devel@patchwork.kernel.org; Wed, 06 Mar 2019 04:07:52 -0500 Received: from eggs.gnu.org ([209.51.188.92]:55205) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h1SGy-0006QW-Dg for qemu-devel@nongnu.org; Wed, 06 Mar 2019 03:51:33 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h1SGs-0001p0-Lj for qemu-devel@nongnu.org; Wed, 06 Mar 2019 03:51:28 -0500 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:52738) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1h1SGo-0001VO-Ow for qemu-devel@nongnu.org; Wed, 06 Mar 2019 03:51:24 -0500 Received: from pps.filterd (m0098393.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x268mUCI040693 for ; Wed, 6 Mar 2019 03:51:02 -0500 Received: from e06smtp02.uk.ibm.com (e06smtp02.uk.ibm.com [195.75.94.98]) by mx0a-001b2d01.pphosted.com with ESMTP id 2r29ye3phc-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Wed, 06 Mar 2019 03:51:02 -0500 Received: from localhost by e06smtp02.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Wed, 6 Mar 2019 08:50:55 -0000 Received: from b06wcsmtp001.portsmouth.uk.ibm.com (b06wcsmtp001.portsmouth.uk.ibm.com [9.149.105.160]) by b06cxnps4076.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x268os2g33816822 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 6 Mar 2019 08:50:55 GMT Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id DCAB2A405B; Wed, 6 Mar 2019 08:50:54 +0000 (GMT) Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id C07F9A4054; Wed, 6 Mar 2019 08:50:54 +0000 (GMT) Received: from smtp.lab.toulouse-stg.fr.ibm.com (unknown [9.101.4.1]) by b06wcsmtp001.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 6 Mar 2019 08:50:54 +0000 (GMT) Received: from zorba.kaod.org.com (sig-9-145-0-135.uk.ibm.com [9.145.0.135]) by smtp.lab.toulouse-stg.fr.ibm.com (Postfix) with ESMTP id 3FC47220158; Wed, 6 Mar 2019 09:50:54 +0100 (CET) From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: David Gibson Date: Wed, 6 Mar 2019 09:50:28 +0100 X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190306085032.15744-1-clg@kaod.org> References: <20190306085032.15744-1-clg@kaod.org> MIME-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 19030608-0008-0000-0000-000002C9253D X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19030608-0009-0000-0000-000022352E9C Message-Id: <20190306085032.15744-24-clg@kaod.org> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-03-06_06:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=2 phishscore=0 bulkscore=0 spamscore=0 clxscore=1034 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1903060061 X-MIME-Autoconverted: from 8bit to quoted-printable by mx0a-001b2d01.pphosted.com id x268mUCI040693 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] X-Received-From: 148.163.156.1 Subject: [Qemu-devel] [PATCH 23/27] ppc/pnv: POWER9 XSCOM quad support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, =?utf-8?q?C=C3=A9dric_Le_Goa?= =?utf-8?q?ter?= Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP The POWER9 processor does not support per-core frequency control. The cores are arranged in groups of four, along with their respective L2 and L3 caches, into a structure known as a Quad. The frequency must be managed at the Quad level. Provide a basic Quad model to fake the settings done by the firmware on the Non-Cacheable Unit (NCU). Each core pair (EX) needs a special BAR setting for the TIMA area of XIVE because it resides on the same address on all chips. Signed-off-by: Cédric Le Goater --- include/hw/ppc/pnv.h | 4 ++ include/hw/ppc/pnv_core.h | 10 +++++ include/hw/ppc/pnv_xscom.h | 12 ++++-- hw/ppc/pnv.c | 38 ++++++++++++++++- hw/ppc/pnv_core.c | 87 ++++++++++++++++++++++++++++++++++++++ 5 files changed, 146 insertions(+), 5 deletions(-) diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index ad3bf0690ecf..04c7125a876d 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -26,6 +26,7 @@ #include "hw/ppc/pnv_psi.h" #include "hw/ppc/pnv_occ.h" #include "hw/ppc/pnv_xive.h" +#include "hw/ppc/pnv_core.h" #define TYPE_PNV_CHIP "pnv-chip" #define PNV_CHIP(obj) OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP) @@ -87,6 +88,9 @@ typedef struct Pnv9Chip { PnvPsi psi; PnvLpcController lpc; PnvOCC occ; + + uint32_t nr_quads; + PnvQuad *quads; } Pnv9Chip; typedef struct PnvChipClass { diff --git a/include/hw/ppc/pnv_core.h b/include/hw/ppc/pnv_core.h index 6874bb847a01..4dcd63660bd1 100644 --- a/include/hw/ppc/pnv_core.h +++ b/include/hw/ppc/pnv_core.h @@ -56,4 +56,14 @@ static inline PnvCPUState *pnv_cpu_state(PowerPCCPU *cpu) return (PnvCPUState *)cpu->machine_data; } +#define TYPE_PNV_QUAD "powernv-cpu-quad" +#define PNV_QUAD(obj) \ + OBJECT_CHECK(PnvQuad, (obj), TYPE_PNV_QUAD) + +typedef struct PnvQuad { + DeviceState parent_obj; + + uint32_t id; + MemoryRegion xscom_regs; +} PnvQuad; #endif /* _PPC_PNV_CORE_H */ diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h index 3292459fbb78..68dfae0dfe41 100644 --- a/include/hw/ppc/pnv_xscom.h +++ b/include/hw/ppc/pnv_xscom.h @@ -60,10 +60,6 @@ typedef struct PnvXScomInterfaceClass { (PNV_XSCOM_EX_CORE_BASE | ((uint64_t)(core) << 24)) #define PNV_XSCOM_EX_SIZE 0x100000 -#define PNV_XSCOM_P9_EC_BASE(core) \ - ((uint64_t)(((core) & 0x1F) + 0x20) << 24) -#define PNV_XSCOM_P9_EC_SIZE 0x100000 - #define PNV_XSCOM_LPC_BASE 0xb0020 #define PNV_XSCOM_LPC_SIZE 0x4 @@ -73,6 +69,14 @@ typedef struct PnvXScomInterfaceClass { #define PNV_XSCOM_OCC_BASE 0x0066000 #define PNV_XSCOM_OCC_SIZE 0x6000 +#define PNV9_XSCOM_EC_BASE(core) \ + ((uint64_t)(((core) & 0x1F) + 0x20) << 24) +#define PNV9_XSCOM_EC_SIZE 0x100000 + +#define PNV9_XSCOM_EQ_BASE(core) \ + ((uint64_t)(((core) & 0x1C) + 0x40) << 22) +#define PNV9_XSCOM_EQ_SIZE 0x100000 + #define PNV9_XSCOM_OCC_BASE PNV_XSCOM_OCC_BASE #define PNV9_XSCOM_OCC_SIZE 0x8000 diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index a056064c8c11..30153ad5acea 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -975,6 +975,36 @@ static void pnv_chip_power9_instance_init(Object *obj) OBJECT(&chip9->psi), &error_abort); } +static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp) +{ + PnvChip *chip = PNV_CHIP(chip9); + const char *typename = pnv_chip_core_typename(chip); + size_t typesize = object_type_get_instance_size(typename); + int i; + + chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); + chip9->quads = g_new0(PnvQuad, chip9->nr_quads); + + for (i = 0; i < chip9->nr_quads; i++) { + char eq_name[32]; + PnvQuad *eq = &chip9->quads[i]; + PnvCore *pnv_core = PNV_CORE(chip->cores + (i * 4) * typesize); + int core_id = CPU_CORE(pnv_core)->core_id; + + object_initialize(eq, sizeof(*eq), TYPE_PNV_QUAD); + snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id); + + object_property_add_child(OBJECT(chip), eq_name, OBJECT(eq), + &error_fatal); + object_property_set_int(OBJECT(eq), core_id, "id", &error_fatal); + object_property_set_bool(OBJECT(eq), true, "realized", &error_fatal); + object_unref(OBJECT(eq)); + + pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->id), + &eq->xscom_regs); + } +} + static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) { PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); @@ -988,6 +1018,12 @@ static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) return; } + pnv_chip_quad_realize(chip9, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + /* XIVE interrupt controller (POWER9) */ object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_IC_BASE(chip), "ic-bar", &error_fatal); @@ -1143,7 +1179,7 @@ static void pnv_chip_core_realize(PnvChip *chip, Error **errp) if (!pnv_chip_is_power9(chip)) { xscom_core_base = PNV_XSCOM_EX_BASE(core_hwid); } else { - xscom_core_base = PNV_XSCOM_P9_EC_BASE(core_hwid); + xscom_core_base = PNV9_XSCOM_EC_BASE(core_hwid); } pnv_xscom_add_subregion(chip, xscom_core_base, diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c index c3d6350dc90a..9e0d87224d5e 100644 --- a/hw/ppc/pnv_core.c +++ b/hw/ppc/pnv_core.c @@ -271,3 +271,90 @@ static const TypeInfo pnv_core_infos[] = { }; DEFINE_TYPES(pnv_core_infos) + +/* + * POWER9 Quads + */ + +#define P9X_EX_NCU_SPEC_BAR 0x11010 + +static uint64_t pnv_quad_xscom_read(void *opaque, hwaddr addr, + unsigned int width) +{ + uint32_t offset = addr >> 3; + uint64_t val = -1; + + switch (offset) { + case P9X_EX_NCU_SPEC_BAR: + case P9X_EX_NCU_SPEC_BAR + 0x400: /* Second EX */ + val = 0; + break; + default: + qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__, + offset); + } + + return val; +} + +static void pnv_quad_xscom_write(void *opaque, hwaddr addr, uint64_t val, + unsigned int width) +{ + uint32_t offset = addr >> 3; + + switch (offset) { + case P9X_EX_NCU_SPEC_BAR: + case P9X_EX_NCU_SPEC_BAR + 0x400: /* Second EX */ + break; + default: + qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__, + offset); + } +} + +static const MemoryRegionOps pnv_quad_xscom_ops = { + .read = pnv_quad_xscom_read, + .write = pnv_quad_xscom_write, + .valid.min_access_size = 8, + .valid.max_access_size = 8, + .impl.min_access_size = 8, + .impl.max_access_size = 8, + .endianness = DEVICE_BIG_ENDIAN, +}; + +static void pnv_quad_realize(DeviceState *dev, Error **errp) +{ + PnvQuad *eq = PNV_QUAD(dev); + char name[32]; + + snprintf(name, sizeof(name), "xscom-quad.%d", eq->id); + pnv_xscom_region_init(&eq->xscom_regs, OBJECT(dev), &pnv_quad_xscom_ops, + eq, name, PNV9_XSCOM_EQ_SIZE); +} + +static Property pnv_quad_properties[] = { + DEFINE_PROP_UINT32("id", PnvQuad, id, 0), + DEFINE_PROP_END_OF_LIST(), +}; + +static void pnv_quad_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + + dc->realize = pnv_quad_realize; + dc->props = pnv_quad_properties; +} + +static const TypeInfo pnv_quad_info = { + .name = TYPE_PNV_QUAD, + .parent = TYPE_DEVICE, + .instance_size = sizeof(PnvQuad), + .class_init = pnv_quad_class_init, +}; + +static void pnv_core_register_types(void) +{ + type_register_static(&pnv_quad_info); +} + +type_init(pnv_core_register_types)