From patchwork Tue Mar 12 08:52:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 10848997 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 13F6F1669 for ; Tue, 12 Mar 2019 10:06:37 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id F366A294F9 for ; Tue, 12 Mar 2019 10:06:36 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E72562952C; Tue, 12 Mar 2019 10:06:36 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 757BE294F9 for ; Tue, 12 Mar 2019 10:06:36 +0000 (UTC) Received: from localhost ([127.0.0.1]:48761 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h3eIt-0005Io-D8 for patchwork-qemu-devel@patchwork.kernel.org; Tue, 12 Mar 2019 06:06:35 -0400 Received: from eggs.gnu.org ([209.51.188.92]:52365) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h3dTw-0007RC-JZ for qemu-devel@nongnu.org; Tue, 12 Mar 2019 05:13:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h3dIS-0006u0-4s for qemu-devel@nongnu.org; Tue, 12 Mar 2019 05:02:09 -0400 Received: from mx1.redhat.com ([209.132.183.28]:48460) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1h3dIR-0006tH-RU; Tue, 12 Mar 2019 05:02:04 -0400 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 2D7D781F31; Tue, 12 Mar 2019 08:54:39 +0000 (UTC) Received: from umbus.redhat.com (vpn2-54-33.bne.redhat.com [10.64.54.33]) by smtp.corp.redhat.com (Postfix) with ESMTP id 76D2B6013E; Tue, 12 Mar 2019 08:54:35 +0000 (UTC) From: David Gibson To: peter.maydell@linaro.org Date: Tue, 12 Mar 2019 19:52:35 +1100 Message-Id: <20190312085316.8054-22-dgibson@redhat.com> In-Reply-To: <20190312085316.8054-1-dgibson@redhat.com> References: <20190312085316.8054-1-dgibson@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.27]); Tue, 12 Mar 2019 08:54:39 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PULL 21/62] ppc/xive: hardwire the Physical CAM line of the thread context X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, clg@kaod.org, qemu-ppc@nongnu.org, qemu-devel@nongnu.org, groug@kaod.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Cédric Le Goater By default on P9, the HW CAM line (23bits) is hardwired to : 0x000||0b1||4Bit chip number||7Bit Thread number. When the block group mode is enabled at the controller level (PowerNV), the CAM line is changed for CAM compares to : 4Bit chip number||0x001||7Bit Thread number This will require changes in xive_presenter_tctx_match() possibly. This is a lowlevel functionality of the HW controller and it is not strictly needed. Leave it for later. Signed-off-by: Cédric Le Goater Message-Id: <20190306085032.15744-2-clg@kaod.org> Signed-off-by: David Gibson --- hw/intc/xive.c | 31 ++++++++++++++++++++++++++++++- 1 file changed, 30 insertions(+), 1 deletion(-) diff --git a/hw/intc/xive.c b/hw/intc/xive.c index daa7badc84..b21759c938 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -1112,6 +1112,30 @@ XiveTCTX *xive_router_get_tctx(XiveRouter *xrtr, CPUState *cs) return xrc->get_tctx(xrtr, cs); } +/* + * By default on P9, the HW CAM line (23bits) is hardwired to : + * + * 0x000||0b1||4Bit chip number||7Bit Thread number. + * + * When the block grouping is enabled, the CAM line is changed to : + * + * 4Bit chip number||0x001||7Bit Thread number. + */ +static uint32_t hw_cam_line(uint8_t chip_id, uint8_t tid) +{ + return 1 << 11 | (chip_id & 0xf) << 7 | (tid & 0x7f); +} + +static bool xive_presenter_tctx_match_hw(XiveTCTX *tctx, + uint8_t nvt_blk, uint32_t nvt_idx) +{ + CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env; + uint32_t pir = env->spr_cb[SPR_PIR].default_value; + + return hw_cam_line((pir >> 8) & 0xf, pir & 0x7f) == + hw_cam_line(nvt_blk, nvt_idx); +} + /* * The thread context register words are in big-endian format. */ @@ -1120,6 +1144,7 @@ static int xive_presenter_tctx_match(XiveTCTX *tctx, uint8_t format, bool cam_ignore, uint32_t logic_serv) { uint32_t cam = xive_nvt_cam_line(nvt_blk, nvt_idx); + uint32_t qw3w2 = xive_tctx_word2(&tctx->regs[TM_QW3_HV_PHYS]); uint32_t qw2w2 = xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]); uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]); uint32_t qw0w2 = xive_tctx_word2(&tctx->regs[TM_QW0_USER]); @@ -1142,7 +1167,11 @@ static int xive_presenter_tctx_match(XiveTCTX *tctx, uint8_t format, /* F=0 & i=0: Specific NVT notification */ - /* TODO (PowerNV) : PHYS ring */ + /* PHYS ring */ + if ((be32_to_cpu(qw3w2) & TM_QW3W2_VT) && + xive_presenter_tctx_match_hw(tctx, nvt_blk, nvt_idx)) { + return TM_QW3_HV_PHYS; + } /* HV POOL ring */ if ((be32_to_cpu(qw2w2) & TM_QW2W2_VP) &&