From patchwork Tue Mar 12 13:15:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 10849285 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4084C1515 for ; Tue, 12 Mar 2019 13:47:44 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 288AA2882D for ; Tue, 12 Mar 2019 13:47:44 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1CE712957B; Tue, 12 Mar 2019 13:47:44 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 5960A2882D for ; Tue, 12 Mar 2019 13:47:43 +0000 (UTC) Received: from localhost ([127.0.0.1]:52831 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h3hks-0001GF-Ev for patchwork-qemu-devel@patchwork.kernel.org; Tue, 12 Mar 2019 09:47:42 -0400 Received: from eggs.gnu.org ([209.51.188.92]:54721) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h3hUc-0002y9-51 for qemu-devel@nongnu.org; Tue, 12 Mar 2019 09:30:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h3hGN-0008HZ-My for qemu-devel@nongnu.org; Tue, 12 Mar 2019 09:16:19 -0400 Received: from mail-pf1-x434.google.com ([2607:f8b0:4864:20::434]:43669) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1h3hGL-00088N-LP for qemu-devel@nongnu.org; Tue, 12 Mar 2019 09:16:11 -0400 Received: by mail-pf1-x434.google.com with SMTP id q17so1802420pfh.10 for ; Tue, 12 Mar 2019 06:16:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding:cc:from:to; bh=tc0PDXayNFl3pTZvWOKGrleXIC3xDndCWcD2Cg/cKdk=; b=I2cWjhm0Sax+0rwBPopQHOm9YQidlwuV0iqpZqwAyaiS4C3QyD+CS9ppqXmOzltnMC YlTEOszO3Nj8mddekujsHQpASh5U2C331tAvwwiVRQOkVI/H/vRsQWdgUQS9+8j5giWq Wv1GQAI5Q9F4Dg/2NXnKKKMKZ3id602j+uOdORg6JOq9TwSlyBNGXf9j6HTRwIm1uVDU cwHImIyV6jTUAWZKkosSQgj7C4LtNPgnJdTc1ZJ2RAE4+wSwGqflJbW/jWNgrrP4q0w+ 2x/IshlXsQ/GzYPy489HTj+6wU8rCO89upEWicNmVMCPD2vDFF1M0rnCFN+94VytSpyx yOnw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:cc:from:to; bh=tc0PDXayNFl3pTZvWOKGrleXIC3xDndCWcD2Cg/cKdk=; b=Gm5MQU6dRpinBRzP7w/v7fd3/YTfjvPHhxQnyjdC8N4srPYVfCrmsSPnY+qIHmIPyj IFsnxl6cO799ALkvF749JcRoi6o0PDhSoqhVnBN1dWfllxtIbf+3ww/AdIpTDHhYTIND aWLw63I2YyNm5mRaLKkjrbJQKUzY6zg3xbZbcw+jMJAmUctJ1JOdYiV1zI6lg6bzZtX3 mpQh//U+JNxnoDNN15XugFtMrHejTjrmEOALU7GhWBaGXPfVEaFMInDZsvx+FI+pQBP1 E9mLuHcAQuIa5u/KXSGxHJixZHVTY31SWENqC/FwiWBYkuGRAebz6JK6Fns6gb7oL3H8 61cQ== X-Gm-Message-State: APjAAAXBzDPSFXsvvbMhzGv1jKS9RmRPzxwLNHv+8H3nPshiSqKPBBNj 06KdRfK0rLW6sDnz9UETUx1m/Y8ZcgDhT2f3 X-Google-Smtp-Source: APXvYqy7MBXa30ogZBZ8zoQQ3PDYLivWqdJhvz9B4OaWMQ+g6QL7nwq3d9XlMWtFVibwdtXHATbrRA== X-Received: by 2002:a63:4e45:: with SMTP id o5mr9339456pgl.220.1552396566764; Tue, 12 Mar 2019 06:16:06 -0700 (PDT) Received: from localhost (2001-b011-7001-120c-5816-f057-fc2f-b780.dynamic-ip6.hinet.net. [2001:b011:7001:120c:5816:f057:fc2f:b780]) by smtp.gmail.com with ESMTPSA id n5sm604749pgp.63.2019.03.12.06.16.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 12 Mar 2019 06:16:05 -0700 (PDT) Date: Tue, 12 Mar 2019 06:15:05 -0700 Message-Id: <20190312131526.14710-9-palmer@sifive.com> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190312131526.14710-1-palmer@sifive.com> References: <20190312131526.14710-1-palmer@sifive.com> MIME-Version: 1.0 From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::434 Subject: [Qemu-devel] [PULL 08/29] target/riscv: Convert RVXM insns to decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bastian Koppelmann , Peer Adelt , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Palmer Dabbelt Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Bastian Koppelmann Acked-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt Signed-off-by: Palmer Dabbelt --- target/riscv/insn32-64.decode | 7 ++ target/riscv/insn32.decode | 10 +++ target/riscv/insn_trans/trans_rvm.inc.c | 113 ++++++++++++++++++++++++ target/riscv/translate.c | 16 ++-- 4 files changed, 137 insertions(+), 9 deletions(-) create mode 100644 target/riscv/insn_trans/trans_rvm.inc.c diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode index 9a35f2aa1920..008f1005469e 100644 --- a/target/riscv/insn32-64.decode +++ b/target/riscv/insn32-64.decode @@ -36,3 +36,10 @@ subw 0100000 ..... ..... 000 ..... 0111011 @r sllw 0000000 ..... ..... 001 ..... 0111011 @r srlw 0000000 ..... ..... 101 ..... 0111011 @r sraw 0100000 ..... ..... 101 ..... 0111011 @r + +# *** RV64M Standard Extension (in addition to RV32M) *** +mulw 0000001 ..... ..... 000 ..... 0111011 @r +divw 0000001 ..... ..... 100 ..... 0111011 @r +divuw 0000001 ..... ..... 101 ..... 0111011 @r +remw 0000001 ..... ..... 110 ..... 0111011 @r +remuw 0000001 ..... ..... 111 ..... 0111011 @r diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 977b1b10a330..e53944bf0e40 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -92,3 +92,13 @@ csrrc ............ ..... 011 ..... 1110011 @csr csrrwi ............ ..... 101 ..... 1110011 @csr csrrsi ............ ..... 110 ..... 1110011 @csr csrrci ............ ..... 111 ..... 1110011 @csr + +# *** RV32M Standard Extension *** +mul 0000001 ..... ..... 000 ..... 0110011 @r +mulh 0000001 ..... ..... 001 ..... 0110011 @r +mulhsu 0000001 ..... ..... 010 ..... 0110011 @r +mulhu 0000001 ..... ..... 011 ..... 0110011 @r +div 0000001 ..... ..... 100 ..... 0110011 @r +divu 0000001 ..... ..... 101 ..... 0110011 @r +rem 0000001 ..... ..... 110 ..... 0110011 @r +remu 0000001 ..... ..... 111 ..... 0110011 @r diff --git a/target/riscv/insn_trans/trans_rvm.inc.c b/target/riscv/insn_trans/trans_rvm.inc.c new file mode 100644 index 000000000000..69631c9e3783 --- /dev/null +++ b/target/riscv/insn_trans/trans_rvm.inc.c @@ -0,0 +1,113 @@ +/* + * RISC-V translation routines for the RV64M Standard Extension. + * + * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu + * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de + * Bastian Koppelmann, kbastian@mail.uni-paderborn.de + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + + +static bool trans_mul(DisasContext *ctx, arg_mul *a) +{ + REQUIRE_EXT(ctx, RVM); + gen_arith(ctx, OPC_RISC_MUL, a->rd, a->rs1, a->rs2); + return true; +} + +static bool trans_mulh(DisasContext *ctx, arg_mulh *a) +{ + REQUIRE_EXT(ctx, RVM); + gen_arith(ctx, OPC_RISC_MULH, a->rd, a->rs1, a->rs2); + return true; +} + +static bool trans_mulhsu(DisasContext *ctx, arg_mulhsu *a) +{ + REQUIRE_EXT(ctx, RVM); + gen_arith(ctx, OPC_RISC_MULHSU, a->rd, a->rs1, a->rs2); + return true; +} + +static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a) +{ + REQUIRE_EXT(ctx, RVM); + gen_arith(ctx, OPC_RISC_MULHU, a->rd, a->rs1, a->rs2); + return true; +} + +static bool trans_div(DisasContext *ctx, arg_div *a) +{ + REQUIRE_EXT(ctx, RVM); + gen_arith(ctx, OPC_RISC_DIV, a->rd, a->rs1, a->rs2); + return true; +} + +static bool trans_divu(DisasContext *ctx, arg_divu *a) +{ + REQUIRE_EXT(ctx, RVM); + gen_arith(ctx, OPC_RISC_DIVU, a->rd, a->rs1, a->rs2); + return true; +} + +static bool trans_rem(DisasContext *ctx, arg_rem *a) +{ + REQUIRE_EXT(ctx, RVM); + gen_arith(ctx, OPC_RISC_REM, a->rd, a->rs1, a->rs2); + return true; +} + +static bool trans_remu(DisasContext *ctx, arg_remu *a) +{ + REQUIRE_EXT(ctx, RVM); + gen_arith(ctx, OPC_RISC_REMU, a->rd, a->rs1, a->rs2); + return true; +} + +#ifdef TARGET_RISCV64 +static bool trans_mulw(DisasContext *ctx, arg_mulw *a) +{ + REQUIRE_EXT(ctx, RVM); + gen_arith(ctx, OPC_RISC_MULW, a->rd, a->rs1, a->rs2); + return true; +} + +static bool trans_divw(DisasContext *ctx, arg_divw *a) +{ + REQUIRE_EXT(ctx, RVM); + gen_arith(ctx, OPC_RISC_DIVW, a->rd, a->rs1, a->rs2); + return true; +} + +static bool trans_divuw(DisasContext *ctx, arg_divuw *a) +{ + REQUIRE_EXT(ctx, RVM); + gen_arith(ctx, OPC_RISC_DIVUW, a->rd, a->rs1, a->rs2); + return true; +} + +static bool trans_remw(DisasContext *ctx, arg_remw *a) +{ + REQUIRE_EXT(ctx, RVM); + gen_arith(ctx, OPC_RISC_REMW, a->rd, a->rs1, a->rs2); + return true; +} + +static bool trans_remuw(DisasContext *ctx, arg_remuw *a) +{ + REQUIRE_EXT(ctx, RVM); + gen_arith(ctx, OPC_RISC_REMUW, a->rd, a->rs1, a->rs2); + return true; +} +#endif diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 18555000af35..783ccade5180 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1841,11 +1841,18 @@ static void decode_RV32_64C(DisasContext *ctx) EX_SH(1) EX_SH(12) +#define REQUIRE_EXT(ctx, ext) do { \ + if (!has_ext(ctx, ext)) { \ + return false; \ + } \ +} while (0) + bool decode_insn32(DisasContext *ctx, uint32_t insn); /* Include the auto-generated decoder for 32 bit insn */ #include "decode_insn32.inc.c" /* Include insn module translation function */ #include "insn_trans/trans_rvi.inc.c" +#include "insn_trans/trans_rvm.inc.c" static void decode_RV32_64G(DisasContext *ctx) { @@ -1867,15 +1874,6 @@ static void decode_RV32_64G(DisasContext *ctx) imm = GET_IMM(ctx->opcode); switch (op) { - case OPC_RISC_ARITH: -#if defined(TARGET_RISCV64) - case OPC_RISC_ARITH_W: -#endif - if (rd == 0) { - break; /* NOP */ - } - gen_arith(ctx, MASK_OP_ARITH(ctx->opcode), rd, rs1, rs2); - break; case OPC_RISC_FP_LOAD: gen_fp_load(ctx, MASK_OP_FP_LOAD(ctx->opcode), rd, rs1, imm); break;