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[2/3] target/arm: cortex-a7 and cortex-a15 have pmus

Message ID 20190322162333.17159-3-drjones@redhat.com (mailing list archive)
State New, archived
Headers show
Series target/arm: pmu fixes | expand

Commit Message

Andrew Jones March 22, 2019, 4:23 p.m. UTC
cortex-a7 and cortex-a15 have pmus (PMUv2) and they advertise
them in ID_DFR0. Let's allow them to function. This also enables
the pmu cpu property to work with these cpu types, i.e. we can
now do '-cpu cortex-a15,pmu=off' to remove the pmu.

Signed-off-by: Andrew Jones <drjones@redhat.com>
---
 target/arm/cpu.c | 3 +++
 1 file changed, 3 insertions(+)

Comments

Aaron Lindsay March 26, 2019, 5:38 p.m. UTC | #1
On Mar 22 17:23, Andrew Jones wrote:
> cortex-a7 and cortex-a15 have pmus (PMUv2) and they advertise
> them in ID_DFR0. Let's allow them to function. This also enables
> the pmu cpu property to work with these cpu types, i.e. we can
> now do '-cpu cortex-a15,pmu=off' to remove the pmu.

I'm a little nervous about this one, but PMUv2 isn't fresh enough in my
mind to have a good reason other than that I didn't consider it when
writing my recent PMU patches. Do you know if this boots a kernel that
can detect and use the PMU successfully while thinking it's PMUv2?

-Aaron

> Signed-off-by: Andrew Jones <drjones@redhat.com>
> ---
>  target/arm/cpu.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/target/arm/cpu.c b/target/arm/cpu.c
> index 96f0ff0ec727..504a4771fbd3 100644
> --- a/target/arm/cpu.c
> +++ b/target/arm/cpu.c
> @@ -1109,6 +1109,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
>  #endif
>      } else {
>          cpu->id_aa64dfr0 &= ~0xf00;
> +        cpu->id_dfr0 &= ~(0xf << 24);
>          cpu->pmceid0 = 0;
>          cpu->pmceid1 = 0;
>      }
> @@ -1744,6 +1745,7 @@ static void cortex_a7_initfn(Object *obj)
>      set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
>      set_feature(&cpu->env, ARM_FEATURE_EL2);
>      set_feature(&cpu->env, ARM_FEATURE_EL3);
> +    set_feature(&cpu->env, ARM_FEATURE_PMU);
>      cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7;
>      cpu->midr = 0x410fc075;
>      cpu->reset_fpsid = 0x41023075;
> @@ -1789,6 +1791,7 @@ static void cortex_a15_initfn(Object *obj)
>      set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
>      set_feature(&cpu->env, ARM_FEATURE_EL2);
>      set_feature(&cpu->env, ARM_FEATURE_EL3);
> +    set_feature(&cpu->env, ARM_FEATURE_PMU);
>      cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
>      cpu->midr = 0x412fc0f1;
>      cpu->reset_fpsid = 0x410430f0;
> -- 
> 2.17.2
>
Andrew Jones March 26, 2019, 5:49 p.m. UTC | #2
On Tue, Mar 26, 2019 at 05:38:36PM +0000, Aaron Lindsay OS wrote:
> On Mar 22 17:23, Andrew Jones wrote:
> > cortex-a7 and cortex-a15 have pmus (PMUv2) and they advertise
> > them in ID_DFR0. Let's allow them to function. This also enables
> > the pmu cpu property to work with these cpu types, i.e. we can
> > now do '-cpu cortex-a15,pmu=off' to remove the pmu.
> 
> I'm a little nervous about this one, but PMUv2 isn't fresh enough in my
> mind to have a good reason other than that I didn't consider it when
> writing my recent PMU patches. Do you know if this boots a kernel that
> can detect and use the PMU successfully while thinking it's PMUv2?
>

I didn't try booting a kernel and running perf or anything like that.
It does now run the pmu kvm-unit-tests test though. As this patch is
now in master the test you propose can be done with a latest build :)

Thanks,
drew
diff mbox series

Patch

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 96f0ff0ec727..504a4771fbd3 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1109,6 +1109,7 @@  static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
 #endif
     } else {
         cpu->id_aa64dfr0 &= ~0xf00;
+        cpu->id_dfr0 &= ~(0xf << 24);
         cpu->pmceid0 = 0;
         cpu->pmceid1 = 0;
     }
@@ -1744,6 +1745,7 @@  static void cortex_a7_initfn(Object *obj)
     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
     set_feature(&cpu->env, ARM_FEATURE_EL2);
     set_feature(&cpu->env, ARM_FEATURE_EL3);
+    set_feature(&cpu->env, ARM_FEATURE_PMU);
     cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7;
     cpu->midr = 0x410fc075;
     cpu->reset_fpsid = 0x41023075;
@@ -1789,6 +1791,7 @@  static void cortex_a15_initfn(Object *obj)
     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
     set_feature(&cpu->env, ARM_FEATURE_EL2);
     set_feature(&cpu->env, ARM_FEATURE_EL3);
+    set_feature(&cpu->env, ARM_FEATURE_PMU);
     cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
     cpu->midr = 0x412fc0f1;
     cpu->reset_fpsid = 0x410430f0;