diff mbox series

[1/5] target/mips: add space to fix checkpatch errors

Message ID 20190403125055.26564-2-jbi.octave@gmail.com (mailing list archive)
State New, archived
Headers show
Series target/mips/cpu: errors and warnings coding style cleanup | expand

Commit Message

Jules Irenge April 3, 2019, 12:50 p.m. UTC
Add space to fix errors reported by checkpatch.pl tool
"ERROR: spaces required around that ..."
"ERROR: space required before the open parenthesis"
"ERROR: space required after that ..."

Signed-off-by: Jules Irenge <jbi.octave@gmail.com>
---
 target/mips/cpu.h | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

Comments

Aleksandar Markovic April 3, 2019, 2:05 p.m. UTC | #1
> From: Jules Irenge <jbi.octave@gmail.com>
> Subject: [PATCH 1/5] target/mips: add space to fix checkpatch errors
> 
> Add space to fix errors reported by checkpatch.pl tool
> "ERROR: spaces required around that ..."
> "ERROR: space required before the open parenthesis"
> "ERROR: space required after that ..."
> 
> Signed-off-by: Jules Irenge <jbi.octave@gmail.com>
> ---
>  target/mips/cpu.h | 20 ++++++++++----------
>  1 file changed, 10 insertions(+), 10 deletions(-)
> 

Hello, Jules.

I appreciate this and all other patches in the series.

It looks that here you have additional types of errors
in the same code lines that you change in this patch
("line over 90 characters"), and this causes the script
checkpatch.pl to report errors for this very patch,
which is not allowed.

I think your best option is to blend (squash) existing
patches 1 and 5 onto a single patch.

> diff --git a/target/mips/cpu.h b/target/mips/cpu.h
> index a10eeb0de3..2429fe80ac 100644
> --- a/target/mips/cpu.h
> +++ b/target/mips/cpu.h
> @@ -22,10 +22,10 @@ typedef struct CPUMIPSTLBContext CPUMIPSTLBContext;
> 
>  typedef union wr_t wr_t;
>  union wr_t {
> -    int8_t  b[MSA_WRLEN/8];
> -    int16_t h[MSA_WRLEN/16];
> -    int32_t w[MSA_WRLEN/32];
> -    int64_t d[MSA_WRLEN/64];
> +    int8_t  b[MSA_WRLEN / 8];
> +    int16_t h[MSA_WRLEN / 16];
> +    int32_t w[MSA_WRLEN / 32];
> +    int64_t d[MSA_WRLEN / 64];
>  };
> 
>  typedef union fpr_t fpr_t;
> @@ -71,16 +71,16 @@ struct CPUMIPSFPUContext {
>  #define FCR31_FS 24
>  #define FCR31_ABS2008 19
>  #define FCR31_NAN2008 18
> -#define SET_FP_COND(num,env)     do { ((env).fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
> -#define CLEAR_FP_COND(num,env)   do { ((env).fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
> +#define SET_FP_COND(num, env)    do { ((env).fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while (0)
> +#define CLEAR_FP_COND(num, env)   do { ((env).fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while (0)

There is a misalignment here for the last two lines, after
this patch is applied ("do" is misaligned). That should be
corrected.

Thanks a lot!
Aleksandar

>  #define GET_FP_COND(env)         ((((env).fcr31 >> 24) & 0xfe) | (((env).fcr31 >> 23) & 0x1))
>  #define GET_FP_CAUSE(reg)        (((reg) >> 12) & 0x3f)
>  #define GET_FP_ENABLE(reg)       (((reg) >>  7) & 0x1f)
>  #define GET_FP_FLAGS(reg)        (((reg) >>  2) & 0x1f)
> -#define SET_FP_CAUSE(reg,v)      do { (reg) = ((reg) & ~(0x3f << 12)) | ((v & 0x3f) << 12); } while(0)
> -#define SET_FP_ENABLE(reg,v)     do { (reg) = ((reg) & ~(0x1f <<  7)) | ((v & 0x1f) << 7); } while(0)
> -#define SET_FP_FLAGS(reg,v)      do { (reg) = ((reg) & ~(0x1f <<  2)) | ((v & 0x1f) << 2); } while(0)
> -#define UPDATE_FP_FLAGS(reg,v)   do { (reg) |= ((v & 0x1f) << 2); } while(0)
> +#define SET_FP_CAUSE(reg, v)      do { (reg) = ((reg) & ~(0x3f << 12)) | ((v & 0x3f) << 12); } while (0)
> +#define SET_FP_ENABLE(reg, v)     do { (reg) = ((reg) & ~(0x1f <<  7)) | ((v & 0x1f) << 7); } while (0)
> +#define SET_FP_FLAGS(reg, v)      do { (reg) = ((reg) & ~(0x1f <<  2)) | ((v & 0x1f) << 2); } while (0)
> +#define UPDATE_FP_FLAGS(reg, v)   do { (reg) |= ((v & 0x1f) << 2); } while (0)
>  #define FP_INEXACT        1
>  #define FP_UNDERFLOW      2
>  #define FP_OVERFLOW       4
> --
> 2.20.1
diff mbox series

Patch

diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index a10eeb0de3..2429fe80ac 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -22,10 +22,10 @@  typedef struct CPUMIPSTLBContext CPUMIPSTLBContext;
 
 typedef union wr_t wr_t;
 union wr_t {
-    int8_t  b[MSA_WRLEN/8];
-    int16_t h[MSA_WRLEN/16];
-    int32_t w[MSA_WRLEN/32];
-    int64_t d[MSA_WRLEN/64];
+    int8_t  b[MSA_WRLEN / 8];
+    int16_t h[MSA_WRLEN / 16];
+    int32_t w[MSA_WRLEN / 32];
+    int64_t d[MSA_WRLEN / 64];
 };
 
 typedef union fpr_t fpr_t;
@@ -71,16 +71,16 @@  struct CPUMIPSFPUContext {
 #define FCR31_FS 24
 #define FCR31_ABS2008 19
 #define FCR31_NAN2008 18
-#define SET_FP_COND(num,env)     do { ((env).fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
-#define CLEAR_FP_COND(num,env)   do { ((env).fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
+#define SET_FP_COND(num, env)    do { ((env).fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while (0)
+#define CLEAR_FP_COND(num, env)   do { ((env).fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while (0)
 #define GET_FP_COND(env)         ((((env).fcr31 >> 24) & 0xfe) | (((env).fcr31 >> 23) & 0x1))
 #define GET_FP_CAUSE(reg)        (((reg) >> 12) & 0x3f)
 #define GET_FP_ENABLE(reg)       (((reg) >>  7) & 0x1f)
 #define GET_FP_FLAGS(reg)        (((reg) >>  2) & 0x1f)
-#define SET_FP_CAUSE(reg,v)      do { (reg) = ((reg) & ~(0x3f << 12)) | ((v & 0x3f) << 12); } while(0)
-#define SET_FP_ENABLE(reg,v)     do { (reg) = ((reg) & ~(0x1f <<  7)) | ((v & 0x1f) << 7); } while(0)
-#define SET_FP_FLAGS(reg,v)      do { (reg) = ((reg) & ~(0x1f <<  2)) | ((v & 0x1f) << 2); } while(0)
-#define UPDATE_FP_FLAGS(reg,v)   do { (reg) |= ((v & 0x1f) << 2); } while(0)
+#define SET_FP_CAUSE(reg, v)      do { (reg) = ((reg) & ~(0x3f << 12)) | ((v & 0x3f) << 12); } while (0)
+#define SET_FP_ENABLE(reg, v)     do { (reg) = ((reg) & ~(0x1f <<  7)) | ((v & 0x1f) << 7); } while (0)
+#define SET_FP_FLAGS(reg, v)      do { (reg) = ((reg) & ~(0x1f <<  2)) | ((v & 0x1f) << 2); } while (0)
+#define UPDATE_FP_FLAGS(reg, v)   do { (reg) |= ((v & 0x1f) << 2); } while (0)
 #define FP_INEXACT        1
 #define FP_UNDERFLOW      2
 #define FP_OVERFLOW       4