From patchwork Tue May 7 16:34:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 10933337 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9BB59912 for ; Tue, 7 May 2019 16:40:47 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 86E6327B2F for ; Tue, 7 May 2019 16:40:47 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 84B47281DB; Tue, 7 May 2019 16:40:47 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 1033227B2F for ; Tue, 7 May 2019 16:40:46 +0000 (UTC) Received: from localhost ([127.0.0.1]:49871 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hO394-0006BP-35 for patchwork-qemu-devel@patchwork.kernel.org; Tue, 07 May 2019 12:40:46 -0400 Received: from eggs.gnu.org ([209.51.188.92]:51636) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hO367-0003by-Ev for qemu-devel@nongnu.org; Tue, 07 May 2019 12:37:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hO366-0004XN-EL for qemu-devel@nongnu.org; Tue, 07 May 2019 12:37:43 -0400 Received: from mx1.redhat.com ([209.132.183.28]:41688) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hO363-0004Te-RM; Tue, 07 May 2019 12:37:40 -0400 Received: from smtp.corp.redhat.com (int-mx08.intmail.prod.int.phx2.redhat.com [10.5.11.23]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id E2751369C4; Tue, 7 May 2019 16:37:38 +0000 (UTC) Received: from x1w.redhat.com (ovpn-204-58.brq.redhat.com [10.40.204.58]) by smtp.corp.redhat.com (Postfix) with ESMTPS id CCAE18164; Tue, 7 May 2019 16:37:29 +0000 (UTC) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Markus Armbruster , Thomas Huth , qemu-devel@nongnu.org, Eduardo Habkost Date: Tue, 7 May 2019 18:34:12 +0200 Message-Id: <20190507163416.24647-13-philmd@redhat.com> In-Reply-To: <20190507163416.24647-1-philmd@redhat.com> References: <20190507163416.24647-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.30]); Tue, 07 May 2019 16:37:39 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH v2 12/16] hw/microblaze/zynqmp: Let the SoC manage the IPI devices X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , "Michael S. Tsirkin" , Antony Pavlov , Paul Burton , Andrew Jeffery , Alistair Francis , Mark Cave-Ayland , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Andrew Baumann , Joel Stanley , Aleksandar Rikalo , qemu-arm@nongnu.org, Peter Chubb , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Aleksandar Markovic , "Edgar E. Iglesias" , qemu-ppc@nongnu.org, Jean-Christophe Dubois , =?utf-8?q?Philippe_Mathieu-Da?= =?utf-8?q?ud=C3=A9?= , Aurelien Jarno , David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP The Inter Processor Interrupt is a block part of the SoC, not the "machine" (See Zynq UltraScale+ Device TRM UG1085, "Platform Management Unit", Power Domains and Islands). Move the IPI management from the machine to the SoC. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Paolo Bonzini Reviewed-by: Alistair Francis --- hw/microblaze/xlnx-zynqmp-pmu.c | 36 +++++++++++++++------------------ 1 file changed, 16 insertions(+), 20 deletions(-) diff --git a/hw/microblaze/xlnx-zynqmp-pmu.c b/hw/microblaze/xlnx-zynqmp-pmu.c index eba9945c19b..20e973edf5f 100644 --- a/hw/microblaze/xlnx-zynqmp-pmu.c +++ b/hw/microblaze/xlnx-zynqmp-pmu.c @@ -68,6 +68,13 @@ static void xlnx_zynqmp_pmu_soc_init(Object *obj) sysbus_init_child_obj(obj, "intc", &s->intc, sizeof(s->intc), TYPE_XLNX_PMU_IO_INTC); + + /* Create the IPI device */ + for (int i = 0; i < XLNX_ZYNQMP_PMU_NUM_IPIS; i++) { + object_initialize(&s->ipi[i], sizeof(XlnxZynqMPIPI), + TYPE_XLNX_ZYNQMP_IPI); + qdev_set_parent_bus(DEVICE(&s->ipi[i]), sysbus_get_default()); + } } static void xlnx_zynqmp_pmu_soc_realize(DeviceState *dev, Error **errp) @@ -113,6 +120,15 @@ static void xlnx_zynqmp_pmu_soc_realize(DeviceState *dev, Error **errp) sysbus_mmio_map(SYS_BUS_DEVICE(&s->intc), 0, XLNX_ZYNQMP_PMU_INTC_ADDR); sysbus_connect_irq(SYS_BUS_DEVICE(&s->intc), 0, qdev_get_gpio_in(DEVICE(&s->cpu), MB_CPU_IRQ)); + + /* Connect the IPI device */ + for (int i = 0; i < XLNX_ZYNQMP_PMU_NUM_IPIS; i++) { + object_property_set_bool(OBJECT(&s->ipi[i]), true, "realized", + &error_abort); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->ipi[i]), 0, ipi_addr[i]); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->ipi[i]), 0, + qdev_get_gpio_in(DEVICE(&s->intc), ipi_irq[i])); + } } static void xlnx_zynqmp_pmu_soc_class_init(ObjectClass *oc, void *data) @@ -145,8 +161,6 @@ static void xlnx_zynqmp_pmu_init(MachineState *machine) MemoryRegion *address_space_mem = get_system_memory(); MemoryRegion *pmu_rom = g_new(MemoryRegion, 1); MemoryRegion *pmu_ram = g_new(MemoryRegion, 1); - qemu_irq irq[32]; - int i; /* Create the ROM */ memory_region_init_rom(pmu_rom, NULL, "xlnx-zynqmp-pmu.rom", @@ -166,24 +180,6 @@ static void xlnx_zynqmp_pmu_init(MachineState *machine) &error_abort); object_property_set_bool(OBJECT(pmu), true, "realized", &error_fatal); - for (i = 0; i < 32; i++) { - irq[i] = qdev_get_gpio_in(DEVICE(&pmu->intc), i); - } - - /* Create and connect the IPI device */ - for (i = 0; i < XLNX_ZYNQMP_PMU_NUM_IPIS; i++) { - object_initialize(&pmu->ipi[i], sizeof(XlnxZynqMPIPI), - TYPE_XLNX_ZYNQMP_IPI); - qdev_set_parent_bus(DEVICE(&pmu->ipi[i]), sysbus_get_default()); - } - - for (i = 0; i < XLNX_ZYNQMP_PMU_NUM_IPIS; i++) { - object_property_set_bool(OBJECT(&pmu->ipi[i]), true, "realized", - &error_abort); - sysbus_mmio_map(SYS_BUS_DEVICE(&pmu->ipi[i]), 0, ipi_addr[i]); - sysbus_connect_irq(SYS_BUS_DEVICE(&pmu->ipi[i]), 0, irq[ipi_irq[i]]); - } - /* Load the kernel */ microblaze_load_kernel(&pmu->cpu, XLNX_ZYNQMP_PMU_RAM_ADDR, machine->ram_size,