From patchwork Fri May 10 20:00:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 10939511 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A569D1390 for ; Fri, 10 May 2019 20:04:56 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8BCD928C84 for ; Fri, 10 May 2019 20:04:56 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 801DB28CCD; Fri, 10 May 2019 20:04:56 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.0 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 02BFF28C84 for ; Fri, 10 May 2019 20:04:54 +0000 (UTC) Received: from localhost ([127.0.0.1]:49309 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hPBlG-0005Jv-5R for patchwork-qemu-devel@patchwork.kernel.org; Fri, 10 May 2019 16:04:54 -0400 Received: from eggs.gnu.org ([209.51.188.92]:33863) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hPBhk-0002SC-K8 for qemu-devel@nongnu.org; Fri, 10 May 2019 16:01:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hPBhi-0002VD-1f for qemu-devel@nongnu.org; Fri, 10 May 2019 16:01:16 -0400 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]:53921) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hPBhd-0002Nq-Se for qemu-devel@nongnu.org; Fri, 10 May 2019 16:01:11 -0400 Received: by mail-wm1-x32e.google.com with SMTP id 198so8678939wme.3 for ; Fri, 10 May 2019 13:01:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=L07Ir53L/bT8njmxfGpI+tM70yQ090QH+043WWisSwk=; b=yiA54U+S+deHa7/+IrX/xbPFaaFsVstt4MONTKcHtTlEUI+jTcaxnaciQhmVzjAQBd 2vMSBBNfDBwnRTAJ19a7VSjtO7P5qPLTB3ZwQM9/iOXieupLWAmQskv531zOHUL0FGkh 3nSNhiZ3uGpOZ9KoPYdWofwefBeG6c2IC0uzLuvxUICxL+ictPrzZ7Au3ht+kRQrMnMB xS2R/1rOZqMs9Q1n4KylHehc0xJqrP5PDOtNmZG3DvWkNFGuIDLmNT0uQWAG3t/Bduh5 OfMmivzZ4o/njMsQi7jg8E7MdCkakfiBU9VOkI9+47EEEQue7qdVG+OfOXZ+Zx8PT2oF xH0Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=L07Ir53L/bT8njmxfGpI+tM70yQ090QH+043WWisSwk=; b=GOzCXlrPoHuWgxB2AH0z2I+GP1wqkJ5OH39Lt8wUJif3q9Dy94yWaR/ES7Q99LIUY1 0nG2UdgWXHNblnrleelJxvg3YBadg2+Gqs80oGrcyfUIKXYWeK+/zFbCH9nx30SbReo/ 1bxlAUigGPz5t8xrF+1m78eYTUi2l/nSS5AGoyCl9IIeCmLCZarAVKdKAByU1xuXhIT+ tIF+uhQ1bibKUz0M9NWNnnBj620vU2MMc3FzK7qaRgEWWz+c2CuC/6f37FzVuf21De82 T/yyC1c0zoamk8Oa5j6vLJcXteF2UL450HO8ieSr/jqyxARBxNlmNleBaagWK9RsW0hi Eezg== X-Gm-Message-State: APjAAAVnHrZTbjn3suZODbYqSk0J4rX+gtM9hIPkBjF81zgxN89BlyUv lXILbSXvW+SCCEi3/iNt/HhRLw== X-Google-Smtp-Source: APXvYqyLAbyiYYDv4OWgAYRGYPJVfhh0GMQMOEeMlhjCFy7K9ZC7wuWF4BuGuR1fIuqzuvULK8W2Ww== X-Received: by 2002:a1c:e904:: with SMTP id q4mr7950555wmc.43.1557518463971; Fri, 10 May 2019 13:01:03 -0700 (PDT) Received: from zen.linaroharston ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id b12sm12868352wrf.21.2019.05.10.13.01.02 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 10 May 2019 13:01:03 -0700 (PDT) Received: from zen.linaroharston. (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 181471FF90; Fri, 10 May 2019 21:01:02 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: peter.maydell@linaro.org Date: Fri, 10 May 2019 21:00:59 +0100 Message-Id: <20190510200101.31096-4-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190510200101.31096-1-alex.bennee@linaro.org> References: <20190510200101.31096-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32e Subject: [Qemu-devel] [PULL 3/5] cputlb: Drop attribute flatten X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , Mark Cave-Ayland , qemu-devel@nongnu.org, Paolo Bonzini , =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Richard Henderson Going to approach this problem via __attribute__((always_inline)) instead, but full conversion will take several steps. Signed-off-by: Richard Henderson Signed-off-by: Alex Bennée Tested-by: Mark Cave-Ayland diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 9c04eb1687c..ccbb47d8d1c 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1291,51 +1291,44 @@ static uint64_t load_helper(CPUArchState *env, target_ulong addr, * We don't bother with this widened value for SOFTMMU_CODE_ACCESS. */ -tcg_target_ulong __attribute__((flatten)) -helper_ret_ldub_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, - uintptr_t retaddr) +tcg_target_ulong helper_ret_ldub_mmu(CPUArchState *env, target_ulong addr, + TCGMemOpIdx oi, uintptr_t retaddr) { return load_helper(env, addr, oi, retaddr, 1, false, false); } -tcg_target_ulong __attribute__((flatten)) -helper_le_lduw_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, - uintptr_t retaddr) +tcg_target_ulong helper_le_lduw_mmu(CPUArchState *env, target_ulong addr, + TCGMemOpIdx oi, uintptr_t retaddr) { return load_helper(env, addr, oi, retaddr, 2, false, false); } -tcg_target_ulong __attribute__((flatten)) -helper_be_lduw_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, - uintptr_t retaddr) +tcg_target_ulong helper_be_lduw_mmu(CPUArchState *env, target_ulong addr, + TCGMemOpIdx oi, uintptr_t retaddr) { return load_helper(env, addr, oi, retaddr, 2, true, false); } -tcg_target_ulong __attribute__((flatten)) -helper_le_ldul_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, - uintptr_t retaddr) +tcg_target_ulong helper_le_ldul_mmu(CPUArchState *env, target_ulong addr, + TCGMemOpIdx oi, uintptr_t retaddr) { return load_helper(env, addr, oi, retaddr, 4, false, false); } -tcg_target_ulong __attribute__((flatten)) -helper_be_ldul_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, - uintptr_t retaddr) +tcg_target_ulong helper_be_ldul_mmu(CPUArchState *env, target_ulong addr, + TCGMemOpIdx oi, uintptr_t retaddr) { return load_helper(env, addr, oi, retaddr, 4, true, false); } -uint64_t __attribute__((flatten)) -helper_le_ldq_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, - uintptr_t retaddr) +uint64_t helper_le_ldq_mmu(CPUArchState *env, target_ulong addr, + TCGMemOpIdx oi, uintptr_t retaddr) { return load_helper(env, addr, oi, retaddr, 8, false, false); } -uint64_t __attribute__((flatten)) -helper_be_ldq_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, - uintptr_t retaddr) +uint64_t helper_be_ldq_mmu(CPUArchState *env, target_ulong addr, + TCGMemOpIdx oi, uintptr_t retaddr) { return load_helper(env, addr, oi, retaddr, 8, true, false); } @@ -1519,51 +1512,44 @@ static void store_helper(CPUArchState *env, target_ulong addr, uint64_t val, } } -void __attribute__((flatten)) -helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val, - TCGMemOpIdx oi, uintptr_t retaddr) +void helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val, + TCGMemOpIdx oi, uintptr_t retaddr) { store_helper(env, addr, val, oi, retaddr, 1, false); } -void __attribute__((flatten)) -helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val, - TCGMemOpIdx oi, uintptr_t retaddr) +void helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val, + TCGMemOpIdx oi, uintptr_t retaddr) { store_helper(env, addr, val, oi, retaddr, 2, false); } -void __attribute__((flatten)) -helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val, - TCGMemOpIdx oi, uintptr_t retaddr) +void helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val, + TCGMemOpIdx oi, uintptr_t retaddr) { store_helper(env, addr, val, oi, retaddr, 2, true); } -void __attribute__((flatten)) -helper_le_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, - TCGMemOpIdx oi, uintptr_t retaddr) +void helper_le_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, + TCGMemOpIdx oi, uintptr_t retaddr) { store_helper(env, addr, val, oi, retaddr, 4, false); } -void __attribute__((flatten)) -helper_be_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, - TCGMemOpIdx oi, uintptr_t retaddr) +void helper_be_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, + TCGMemOpIdx oi, uintptr_t retaddr) { store_helper(env, addr, val, oi, retaddr, 4, true); } -void __attribute__((flatten)) -helper_le_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, - TCGMemOpIdx oi, uintptr_t retaddr) +void helper_le_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, + TCGMemOpIdx oi, uintptr_t retaddr) { store_helper(env, addr, val, oi, retaddr, 8, false); } -void __attribute__((flatten)) -helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, - TCGMemOpIdx oi, uintptr_t retaddr) +void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, + TCGMemOpIdx oi, uintptr_t retaddr) { store_helper(env, addr, val, oi, retaddr, 8, true); } @@ -1627,51 +1613,44 @@ helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, /* Code access functions. */ -uint8_t __attribute__((flatten)) -helper_ret_ldb_cmmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, - uintptr_t retaddr) +uint8_t helper_ret_ldb_cmmu(CPUArchState *env, target_ulong addr, + TCGMemOpIdx oi, uintptr_t retaddr) { return load_helper(env, addr, oi, retaddr, 1, false, true); } -uint16_t __attribute__((flatten)) -helper_le_ldw_cmmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, - uintptr_t retaddr) +uint16_t helper_le_ldw_cmmu(CPUArchState *env, target_ulong addr, + TCGMemOpIdx oi, uintptr_t retaddr) { return load_helper(env, addr, oi, retaddr, 2, false, true); } -uint16_t __attribute__((flatten)) -helper_be_ldw_cmmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, - uintptr_t retaddr) +uint16_t helper_be_ldw_cmmu(CPUArchState *env, target_ulong addr, + TCGMemOpIdx oi, uintptr_t retaddr) { return load_helper(env, addr, oi, retaddr, 2, true, true); } -uint32_t __attribute__((flatten)) -helper_le_ldl_cmmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, - uintptr_t retaddr) +uint32_t helper_le_ldl_cmmu(CPUArchState *env, target_ulong addr, + TCGMemOpIdx oi, uintptr_t retaddr) { return load_helper(env, addr, oi, retaddr, 4, false, true); } -uint32_t __attribute__((flatten)) -helper_be_ldl_cmmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, - uintptr_t retaddr) +uint32_t helper_be_ldl_cmmu(CPUArchState *env, target_ulong addr, + TCGMemOpIdx oi, uintptr_t retaddr) { return load_helper(env, addr, oi, retaddr, 4, true, true); } -uint64_t __attribute__((flatten)) -helper_le_ldq_cmmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, - uintptr_t retaddr) +uint64_t helper_le_ldq_cmmu(CPUArchState *env, target_ulong addr, + TCGMemOpIdx oi, uintptr_t retaddr) { return load_helper(env, addr, oi, retaddr, 8, false, true); } -uint64_t __attribute__((flatten)) -helper_be_ldq_cmmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, - uintptr_t retaddr) +uint64_t helper_be_ldq_cmmu(CPUArchState *env, target_ulong addr, + TCGMemOpIdx oi, uintptr_t retaddr) { return load_helper(env, addr, oi, retaddr, 8, true, true); }