From patchwork Fri May 17 10:21:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Hildenbrand X-Patchwork-Id: 10947709 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1091414C0 for ; Fri, 17 May 2019 10:44:05 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id F338926E3C for ; Fri, 17 May 2019 10:44:04 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E503226E3E; Fri, 17 May 2019 10:44:04 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 57C0B26E3C for ; Fri, 17 May 2019 10:44:04 +0000 (UTC) Received: from localhost ([127.0.0.1]:46111 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hRaLL-0002lh-Kr for patchwork-qemu-devel@patchwork.kernel.org; Fri, 17 May 2019 06:44:03 -0400 Received: from eggs.gnu.org ([209.51.188.92]:49394) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hRa6R-0006TZ-ET for qemu-devel@nongnu.org; Fri, 17 May 2019 06:28:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hRa1m-0005E5-Ec for qemu-devel@nongnu.org; Fri, 17 May 2019 06:23:51 -0400 Received: from mx1.redhat.com ([209.132.183.28]:40314) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hRa1m-0005DI-6g; Fri, 17 May 2019 06:23:50 -0400 Received: from smtp.corp.redhat.com (int-mx08.intmail.prod.int.phx2.redhat.com [10.5.11.23]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 799A330832E4; Fri, 17 May 2019 10:23:49 +0000 (UTC) Received: from t460s.redhat.com (unknown [10.36.118.100]) by smtp.corp.redhat.com (Postfix) with ESMTP id 017A338E01; Fri, 17 May 2019 10:23:47 +0000 (UTC) From: David Hildenbrand To: qemu-devel@nongnu.org Date: Fri, 17 May 2019 12:21:31 +0200 Message-Id: <20190517102145.21812-27-david@redhat.com> In-Reply-To: <20190517102145.21812-1-david@redhat.com> References: <20190517102145.21812-1-david@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.44]); Fri, 17 May 2019 10:23:49 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PULL SUBSYSTEM s390x 26/40] s390x/tcg: Implement VECTOR ELEMENT ROTATE LEFT LOGICAL X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , David Hildenbrand , Cornelia Huck , Richard Henderson , qemu-s390x@nongnu.org, Richard Henderson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Take care of properly taking the modulo of the count. We might later want to come back and create a variant of VERLL where the base register is 0, resulting in an immediate. Reviewed-by: Richard Henderson Signed-off-by: David Hildenbrand --- target/s390x/helper.h | 4 +++ target/s390x/insn-data.def | 3 ++ target/s390x/translate_vx.inc.c | 60 +++++++++++++++++++++++++++++++++ target/s390x/vec_int_helper.c | 31 +++++++++++++++++ 4 files changed, 98 insertions(+) diff --git a/target/s390x/helper.h b/target/s390x/helper.h index 20b677917b..b3e15cfe8c 100644 --- a/target/s390x/helper.h +++ b/target/s390x/helper.h @@ -198,6 +198,10 @@ DEF_HELPER_FLAGS_4(gvec_vmlo16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32) DEF_HELPER_FLAGS_4(gvec_vmlo32, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32) DEF_HELPER_FLAGS_3(gvec_vpopct8, TCG_CALL_NO_RWG, void, ptr, cptr, i32) DEF_HELPER_FLAGS_3(gvec_vpopct16, TCG_CALL_NO_RWG, void, ptr, cptr, i32) +DEF_HELPER_FLAGS_4(gvec_verllv8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32) +DEF_HELPER_FLAGS_4(gvec_verllv16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32) +DEF_HELPER_FLAGS_4(gvec_verll8, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32) +DEF_HELPER_FLAGS_4(gvec_verll16, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32) #ifndef CONFIG_USER_ONLY DEF_HELPER_3(servc, i32, env, i64, i64) diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def index 0f786d6ab1..e765c15941 100644 --- a/target/s390x/insn-data.def +++ b/target/s390x/insn-data.def @@ -1146,6 +1146,9 @@ F(0xe76f, VOC, VRR_c, VE, 0, 0, 0, 0, voc, 0, IF_VEC) /* VECTOR POPULATION COUNT */ F(0xe750, VPOPCT, VRR_a, V, 0, 0, 0, 0, vpopct, 0, IF_VEC) +/* VECTOR ELEMENT ROTATE LEFT LOGICAL */ + F(0xe773, VERLLV, VRR_c, V, 0, 0, 0, 0, verllv, 0, IF_VEC) + F(0xe733, VERLL, VRS_a, V, la2, 0, 0, 0, verll, 0, IF_VEC) #ifndef CONFIG_USER_ONLY /* COMPARE AND SWAP AND PURGE */ diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c index 7e4876247e..0ca3bb3e6a 100644 --- a/target/s390x/translate_vx.inc.c +++ b/target/s390x/translate_vx.inc.c @@ -185,6 +185,9 @@ static void get_vec_element_ptr_i64(TCGv_ptr ptr, uint8_t reg, TCGv_i64 enr, #define gen_gvec_2(v1, v2, gen) \ tcg_gen_gvec_2(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \ 16, 16, gen) +#define gen_gvec_2s(v1, v2, c, gen) \ + tcg_gen_gvec_2s(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \ + 16, 16, c, gen) #define gen_gvec_3(v1, v2, v3, gen) \ tcg_gen_gvec_3(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \ vec_full_reg_offset(v3), 16, 16, gen) @@ -1845,3 +1848,60 @@ static DisasJumpType op_vpopct(DisasContext *s, DisasOps *o) gen_gvec_2(get_field(s->fields, v1), get_field(s->fields, v2), &g[es]); return DISAS_NEXT; } + +static void gen_rll_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) +{ + TCGv_i32 t0 = tcg_temp_new_i32(); + + tcg_gen_andi_i32(t0, b, 31); + tcg_gen_rotl_i32(d, a, t0); + tcg_temp_free_i32(t0); +} + +static void gen_rll_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) +{ + TCGv_i64 t0 = tcg_temp_new_i64(); + + tcg_gen_andi_i64(t0, b, 63); + tcg_gen_rotl_i64(d, a, t0); + tcg_temp_free_i64(t0); +} + +static DisasJumpType op_verllv(DisasContext *s, DisasOps *o) +{ + const uint8_t es = get_field(s->fields, m4); + static const GVecGen3 g[4] = { + { .fno = gen_helper_gvec_verllv8, }, + { .fno = gen_helper_gvec_verllv16, }, + { .fni4 = gen_rll_i32, }, + { .fni8 = gen_rll_i64, }, + }; + + if (es > ES_64) { + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } + + gen_gvec_3(get_field(s->fields, v1), get_field(s->fields, v2), + get_field(s->fields, v3), &g[es]); + return DISAS_NEXT; +} + +static DisasJumpType op_verll(DisasContext *s, DisasOps *o) +{ + const uint8_t es = get_field(s->fields, m4); + static const GVecGen2s g[4] = { + { .fno = gen_helper_gvec_verll8, }, + { .fno = gen_helper_gvec_verll16, }, + { .fni4 = gen_rll_i32, }, + { .fni8 = gen_rll_i64, }, + }; + + if (es > ES_64) { + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } + gen_gvec_2s(get_field(s->fields, v1), get_field(s->fields, v3), o->addr1, + &g[es]); + return DISAS_NEXT; +} diff --git a/target/s390x/vec_int_helper.c b/target/s390x/vec_int_helper.c index fd8162f1f1..a3c8f09eac 100644 --- a/target/s390x/vec_int_helper.c +++ b/target/s390x/vec_int_helper.c @@ -478,3 +478,34 @@ void HELPER(gvec_vpopct##BITS)(void *v1, const void *v2, uint32_t desc) \ } DEF_VPOPCT(8) DEF_VPOPCT(16) + +#define DEF_VERLLV(BITS) \ +void HELPER(gvec_verllv##BITS)(void *v1, const void *v2, const void *v3, \ + uint32_t desc) \ +{ \ + int i; \ + \ + for (i = 0; i < (128 / BITS); i++) { \ + const uint##BITS##_t a = s390_vec_read_element##BITS(v2, i); \ + const uint##BITS##_t b = s390_vec_read_element##BITS(v3, i); \ + \ + s390_vec_write_element##BITS(v1, i, rol##BITS(a, b)); \ + } \ +} +DEF_VERLLV(8) +DEF_VERLLV(16) + +#define DEF_VERLL(BITS) \ +void HELPER(gvec_verll##BITS)(void *v1, const void *v2, uint64_t count, \ + uint32_t desc) \ +{ \ + int i; \ + \ + for (i = 0; i < (128 / BITS); i++) { \ + const uint##BITS##_t a = s390_vec_read_element##BITS(v2, i); \ + \ + s390_vec_write_element##BITS(v1, i, rol##BITS(a, count)); \ + } \ +} +DEF_VERLL(8) +DEF_VERLL(16)