From patchwork Fri May 24 06:35:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 10959161 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EFE7114C0 for ; Fri, 24 May 2019 06:41:36 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DDF52287E6 for ; Fri, 24 May 2019 06:41:36 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D278F2881A; Fri, 24 May 2019 06:41:36 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 74C9A287E6 for ; Fri, 24 May 2019 06:41:36 +0000 (UTC) Received: from localhost ([127.0.0.1]:49769 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hU3tX-0006kR-NM for patchwork-qemu-devel@patchwork.kernel.org; Fri, 24 May 2019 02:41:35 -0400 Received: from eggs.gnu.org ([209.51.188.92]:40855) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hU3ph-0003R2-Uc for qemu-devel@nongnu.org; Fri, 24 May 2019 02:37:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hU3ph-0003Jw-0E for qemu-devel@nongnu.org; Fri, 24 May 2019 02:37:37 -0400 Received: from mx1.redhat.com ([209.132.183.28]:37156) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hU3pg-0003JZ-P1 for qemu-devel@nongnu.org; Fri, 24 May 2019 02:37:36 -0400 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 0E6A8C0578C4; Fri, 24 May 2019 06:37:36 +0000 (UTC) Received: from x1w.redhat.com (ovpn-204-235.brq.redhat.com [10.40.204.235]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 758F65B689; Fri, 24 May 2019 06:37:32 +0000 (UTC) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Date: Fri, 24 May 2019 08:35:45 +0200 Message-Id: <20190524063553.5339-13-philmd@redhat.com> In-Reply-To: <20190524063553.5339-1-philmd@redhat.com> References: <20190524063553.5339-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.31]); Fri, 24 May 2019 06:37:36 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH 12/20] hw/i386/pc: Pass the CPUArchIdList array by argument X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yang Zhong , Eduardo Habkost , Rob Bradford , "Michael S. Tsirkin" , Marcelo Tosatti , Paolo Bonzini , Richard Henderson , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Samuel Ortiz Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Pass the CPUArchIdList array by argument, this will allow us to remove the PCMachineState argument later. Suggested-by: Samuel Ortiz Signed-off-by: Philippe Mathieu-Daudé --- hw/i386/pc.c | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index fe07baeb1d..6cfdb09f34 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -928,14 +928,12 @@ static void pc_build_smbios(PCMachineState *pcms) } } -static FWCfgState *x86_create_fw_cfg(PCMachineState *pcms, +static FWCfgState *x86_create_fw_cfg(PCMachineState *pcms, const CPUArchIdList *cpus, uint16_t boot_cpus, uint16_t apic_id_limit) { FWCfgState *fw_cfg; uint64_t *numa_fw_cfg; int i; - const CPUArchIdList *cpus; - MachineClass *mc = MACHINE_GET_CLASS(pcms); fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4, &address_space_memory); @@ -953,7 +951,7 @@ static FWCfgState *x86_create_fw_cfg(PCMachineState *pcms, * So for compatibility reasons with old BIOSes we are stuck with * "etc/max-cpus" actually being apic_id_limit */ - fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)pcms->apic_id_limit); + fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, apic_id_limit); fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, acpi_tables, acpi_tables_len); @@ -969,20 +967,19 @@ static FWCfgState *x86_create_fw_cfg(PCMachineState *pcms, * of nodes, one word for each VCPU->node and one word for each node to * hold the amount of memory. */ - numa_fw_cfg = g_new0(uint64_t, 1 + pcms->apic_id_limit + nb_numa_nodes); + numa_fw_cfg = g_new0(uint64_t, 1 + apic_id_limit + nb_numa_nodes); numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes); - cpus = mc->possible_cpu_arch_ids(MACHINE(pcms)); for (i = 0; i < cpus->len; i++) { unsigned int apic_id = cpus->cpus[i].arch_id; - assert(apic_id < pcms->apic_id_limit); + assert(apic_id < apic_id_limit); numa_fw_cfg[apic_id + 1] = cpu_to_le64(cpus->cpus[i].props.node_id); } for (i = 0; i < nb_numa_nodes; i++) { - numa_fw_cfg[pcms->apic_id_limit + 1 + i] = + numa_fw_cfg[apic_id_limit + 1 + i] = cpu_to_le64(numa_info[i].node_mem); } fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg, - (1 + pcms->apic_id_limit + nb_numa_nodes) * + (1 + apic_id_limit + nb_numa_nodes) * sizeof(*numa_fw_cfg)); return fw_cfg; @@ -1763,7 +1760,8 @@ void pc_memory_init(PCMachineState *pcms, option_rom_mr, 1); - fw_cfg = x86_create_fw_cfg(pcms, pcms->boot_cpus, pcms->apic_id_limit); + fw_cfg = x86_create_fw_cfg(pcms, mc->possible_cpu_arch_ids(machine), + pcms->boot_cpus, pcms->apic_id_limit); rom_set_fw(fw_cfg);