From patchwork Fri May 24 06:35:37 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 10959171 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D86201395 for ; Fri, 24 May 2019 06:45:40 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C589F287E7 for ; Fri, 24 May 2019 06:45:40 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B95C22881A; Fri, 24 May 2019 06:45:40 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 5C4AF287E7 for ; Fri, 24 May 2019 06:45:40 +0000 (UTC) Received: from localhost ([127.0.0.1]:49836 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hU3xT-0001ex-4Y for patchwork-qemu-devel@patchwork.kernel.org; Fri, 24 May 2019 02:45:39 -0400 Received: from eggs.gnu.org ([209.51.188.92]:40622) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hU3ol-0002mR-R3 for qemu-devel@nongnu.org; Fri, 24 May 2019 02:36:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hU3ok-0002qN-PD for qemu-devel@nongnu.org; Fri, 24 May 2019 02:36:39 -0400 Received: from mx1.redhat.com ([209.132.183.28]:48490) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hU3ok-0002qB-Hu for qemu-devel@nongnu.org; Fri, 24 May 2019 02:36:38 -0400 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id D2958307D91E; Fri, 24 May 2019 06:36:37 +0000 (UTC) Received: from x1w.redhat.com (ovpn-204-235.brq.redhat.com [10.40.204.235]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 638CD5B689; Fri, 24 May 2019 06:36:33 +0000 (UTC) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Date: Fri, 24 May 2019 08:35:37 +0200 Message-Id: <20190524063553.5339-5-philmd@redhat.com> In-Reply-To: <20190524063553.5339-1-philmd@redhat.com> References: <20190524063553.5339-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.48]); Fri, 24 May 2019 06:36:37 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH 04/20] hw/i386/pc: Add the E820Type enum type X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yang Zhong , Eduardo Habkost , Rob Bradford , "Michael S. Tsirkin" , Marcelo Tosatti , Paolo Bonzini , Richard Henderson , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Samuel Ortiz Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP This ensure we won't use an incorrect value. Signed-off-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé --- hw/i386/pc.c | 12 +++++++----- include/hw/i386/pc.h | 16 ++++++++++------ 2 files changed, 17 insertions(+), 11 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 1245028dd6..ac8343c728 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -868,9 +868,10 @@ static void handle_a20_line_change(void *opaque, int irq, int level) x86_cpu_set_a20(cpu, level); } -ssize_t e820_add_entry(uint64_t address, uint64_t length, uint32_t type) +ssize_t e820_add_entry(uint64_t address, uint64_t length, E820Type type) { unsigned int index = le32_to_cpu(e820_reserve.count); + uint32_t utype = (uint32_t)type; struct e820_entry *entry; if (type != E820_RAM) { @@ -882,7 +883,7 @@ ssize_t e820_add_entry(uint64_t address, uint64_t length, uint32_t type) entry->address = cpu_to_le64(address); entry->length = cpu_to_le64(length); - entry->type = cpu_to_le32(type); + entry->type = cpu_to_le32(utype); e820_reserve.count = cpu_to_le32(index); } @@ -891,7 +892,7 @@ ssize_t e820_add_entry(uint64_t address, uint64_t length, uint32_t type) e820_table = g_renew(struct e820_entry, e820_table, e820_entries + 1); e820_table[e820_entries].address = cpu_to_le64(address); e820_table[e820_entries].length = cpu_to_le64(length); - e820_table[e820_entries].type = cpu_to_le32(type); + e820_table[e820_entries].type = cpu_to_le32(utype); e820_entries++; return e820_entries; @@ -902,10 +903,11 @@ size_t e820_get_num_entries(void) return e820_entries; } -bool e820_get_entry(unsigned int idx, uint32_t type, +bool e820_get_entry(unsigned int idx, E820Type type, uint64_t *address, uint64_t *length) { - if (idx < e820_entries && e820_table[idx].type == cpu_to_le32(type)) { + uint32_t utype = (uint32_t)type; + if (idx < e820_entries && e820_table[idx].type == cpu_to_le32(utype)) { *address = le64_to_cpu(e820_table[idx].address); *length = le64_to_cpu(e820_table[idx].length); return true; diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index 2bc48c03c6..10e77a40ce 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -282,12 +282,16 @@ void pc_system_firmware_init(PCMachineState *pcms, MemoryRegion *rom_memory); void pc_madt_cpu_entry(AcpiDeviceIf *adev, int uid, const CPUArchIdList *apic_ids, GArray *entry); -/* e820 types */ -#define E820_RAM 1 -#define E820_RESERVED 2 -#define E820_ACPI 3 -#define E820_NVS 4 -#define E820_UNUSABLE 5 +/** + * E820Type: Type of the e820 address range. + */ +typedef enum { + E820_RAM = 1, + E820_RESERVED = 2, + E820_ACPI = 3, + E820_NVS = 4, + E820_UNUSABLE = 5 +} E820Type; ssize_t e820_add_entry(uint64_t, uint64_t, uint32_t); size_t e820_get_num_entries(void);