diff mbox series

[04/42] target/arm: Fix Cortex-R5F MVFR values

Message ID 20190606174609.20487-5-peter.maydell@linaro.org (mailing list archive)
State New, archived
Headers show
Series target/arm: Convert VFP decoder to decodetree | expand

Commit Message

Peter Maydell June 6, 2019, 5:45 p.m. UTC
The Cortex-R5F initfn was not correctly setting up the MVFR
ID register values. Fill these in, since some subsequent patches
will use ID register checks rather than CPU feature bit checks.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.c | 2 ++
 1 file changed, 2 insertions(+)

Comments

Richard Henderson June 7, 2019, 2:50 p.m. UTC | #1
On 6/6/19 12:45 PM, Peter Maydell wrote:
> The Cortex-R5F initfn was not correctly setting up the MVFR
> ID register values. Fill these in, since some subsequent patches
> will use ID register checks rather than CPU feature bit checks.
> 
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
>  target/arm/cpu.c | 2 ++
>  1 file changed, 2 insertions(+)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~
diff mbox series

Patch

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 9b23ac2c935..044c4dd738b 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1608,6 +1608,8 @@  static void cortex_r5f_initfn(Object *obj)
 
     cortex_r5_initfn(obj);
     set_feature(&cpu->env, ARM_FEATURE_VFP3);
+    cpu->isar.mvfr0 = 0x10110221;
+    cpu->isar.mvfr1 = 0x00000011;
 }
 
 static const ARMCPRegInfo cortexa8_cp_reginfo[] = {