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[67.9.99.67]) by smtp.gmail.com with ESMTPSA id e12sm1714426ywe.85.2019.06.18.22.05.07 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Tue, 18 Jun 2019 22:05:07 -0700 (PDT) From: Jan Bobek To: qemu-devel@nongnu.org Date: Wed, 19 Jun 2019 01:04:46 -0400 Message-Id: <20190619050447.22201-7-jan.bobek@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190619050447.22201-1-jan.bobek@gmail.com> References: <20190619050447.22201-1-jan.bobek@gmail.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::b44 Subject: [Qemu-devel] [RISU RFC PATCH v1 6/7] x86.risu: add SSE instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jan Bobek , =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Add an x86 configuration file with all SSE instructions. Signed-off-by: Jan Bobek --- x86.risu | 99 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 99 insertions(+) create mode 100644 x86.risu diff --git a/x86.risu b/x86.risu new file mode 100644 index 0000000..cc40bbc --- /dev/null +++ b/x86.risu @@ -0,0 +1,99 @@ +############################################################################### +# Copyright (c) 2019 Linaro Limited +# All rights reserved. This program and the accompanying materials +# are made available under the terms of the Eclipse Public License v1.0 +# which accompanies this distribution, and is available at +# http://www.eclipse.org/legal/epl-v10.html +# +# Contributors: +# Jan Bobek - initial implementation +############################################################################### + +# Input file for risugen defining x86 instructions +.mode x86 + +# SSE Data Transfer Instructions +MOVUPS SSE 00001111 0001000 d !emit { modrm(); mem(size => 16); } +MOVSS SSE 00001111 0001000 d !emit { rep(); modrm(); mem(size => 4); } +MOVHLPS SSE 00001111 00010010 !emit { modrm(mod => MOD_DIRECT); } +MOVLPS SSE 00001111 0001001 d !emit { modrm(mod => ~MOD_DIRECT); mem(size => 8); } +MOVLHPS SSE 00001111 00010110 !emit { modrm(mod => MOD_DIRECT); } +MOVHPS SSE 00001111 0001011 d !emit { modrm(mod => ~MOD_DIRECT); mem(size => 8); } +MOVAPS SSE 00001111 0010100 d !emit { modrm(); mem(size => 16, align => 16); } +MOVMSKPS SSE 00001111 01010000 !emit { modrm(mod => MOD_DIRECT, reg => ~REG_ESP); } + +# SSE Packed Arithmetic Instructions +ADDPS SSE 00001111 01011000 !emit { modrm(); mem(size => 16, align => 16); } +ADDSS SSE 00001111 01011000 !emit { rep(); modrm(); mem(size => 4); } +SUBPS SSE 00001111 01011100 !emit { modrm(); mem(size => 16, align => 16); } +SUBSS SSE 00001111 01011100 !emit { rep(); modrm(); mem(size => 4); } +MULPS SSE 00001111 01011001 !emit { modrm(); mem(size => 16, align => 16); } +MULSS SSE 00001111 01011001 !emit { rep(); modrm(); mem(size => 4); } +DIVPS SSE 00001111 01011110 !emit { modrm(); mem(size => 16, align => 16); } +DIVSS SSE 00001111 01011110 !emit { rep(); modrm(); mem(size => 4); } +RCPPS SSE 00001111 01010011 !emit { modrm(); mem(size => 16, align => 16); } +RCPSS SSE 00001111 01010011 !emit { rep(); modrm(); mem(size => 4); } +SQRTPS SSE 00001111 01010001 !emit { modrm(); mem(size => 16, align => 16); } +SQRTSS SSE 00001111 01010001 !emit { rep(); modrm(); mem(size => 4); } +RSQRTPS SSE 00001111 01010010 !emit { modrm(); mem(size => 16, align => 16); } +RSQRTSS SSE 00001111 01010010 !emit { rep(); modrm(); mem(size => 4); } +MINPS SSE 00001111 01011101 !emit { modrm(); mem(size => 16, align => 16); } +MINSS SSE 00001111 01011101 !emit { rep(); modrm(); mem(size => 4); } +MAXPS SSE 00001111 01011111 !emit { modrm(); mem(size => 16, align => 16); } +MAXSS SSE 00001111 01011111 !emit { rep(); modrm(); mem(size => 4); } + +# SSE Comparison Instructions +CMPPS SSE 00001111 11000010 !emit { modrm(); mem(size => 16, align => 16); imm(size => 1); } +CMPSS SSE 00001111 11000010 !emit { rep(); modrm(); mem(size => 4); imm(size => 1); } +UCOMISS SSE 00001111 00101110 !emit { modrm(); mem(size => 4); } +COMISS SSE 00001111 00101111 !emit { modrm(); mem(size => 4); } + +# SSE Logical Instructions +ANDPS SSE 00001111 01010100 !emit { modrm(); mem(size => 16, align => 16); } +ANDNPS SSE 00001111 01010101 !emit { modrm(); mem(size => 16, align => 16); } +ORPS SSE 00001111 01010110 !emit { modrm(); mem(size => 16, align => 16); } +XORPS SSE 00001111 01010111 !emit { modrm(); mem(size => 16, align => 16); } + +# SSE Shuffle and Unpack Instructions +SHUFPS SSE 00001111 11000110 !emit { modrm(); mem(size => 16, align => 16); imm(size => 1); } +UNPCKLPS SSE 00001111 00010100 !emit { modrm(); mem(size => 16, align => 16); } +UNPCKHPS SSE 00001111 00010101 !emit { modrm(); mem(size => 16, align => 16); } + +# SSE Conversion Instructions +CVTPI2PS SSE 00001111 00101010 !emit { modrm(); mem(size => 8); } +CVTSI2SS SSE 00001111 00101010 !emit { rep(); modrm(); mem(size => 4); } +CVTSI2SS_64 SSE 00001111 00101010 !emit { rep(); rex(w => 1); modrm(); mem(size => 8); } +CVTPS2PI SSE 00001111 00101101 !emit { modrm(); mem(size => 8); } +CVTSS2SI SSE 00001111 00101101 !emit { rep(); modrm(reg => ~REG_ESP); mem(size => 4); } +CVTSS2SI_64 SSE 00001111 00101101 !emit { rep(); rex(w => 1); modrm(reg => ~REG_ESP); mem(size => 4); } +CVTTPS2PI SSE 00001111 00101100 !emit { modrm(); mem(size => 8); } +CVTTSS2SI SSE 00001111 00101100 !emit { rep(); modrm(reg => ~REG_ESP); mem(size => 4); } +CVTTSS2SI_64 SSE 00001111 00101100 !emit { rep(); rex(w => 1); modrm(reg => ~REG_ESP); mem(size => 4); } + +# SSE MXCSR State Management Instructions +# LDMXCSR SSE 00001111 10101110 !emit { modrm(mod => ~MOD_DIRECT, reg => 2); mem(size => 4); } +STMXCSR SSE 00001111 10101110 !emit { modrm(mod => ~MOD_DIRECT, reg => 3); mem(size => 4); } + +# SSE 64-bit SIMD Integer Instructions +PAVGB SSE 00001111 11100000 !emit { modrm(); mem(size => 8); } +PAVGW SSE 00001111 11100011 !emit { modrm(); mem(size => 8); } +PEXTRW SSE 00001111 11000101 !emit { modrm(mod => MOD_DIRECT, reg => ~REG_ESP); mem(size => 8); imm(size => 1); } +PINSRW SSE 00001111 11000100 !emit { modrm(); mem(size => 2); imm(size => 1); } +PMAXUB SSE 00001111 11011110 !emit { modrm(); mem(size => 8); } +PMAXSW SSE 00001111 11101110 !emit { modrm(); mem(size => 8); } +PMINUB SSE 00001111 11011010 !emit { modrm(); mem(size => 8); } +PMINSW SSE 00001111 11101010 !emit { modrm(); mem(size => 8); } +PMOVMSKB SSE 00001111 11010111 !emit { modrm(mod => MOD_DIRECT, reg => ~REG_ESP); mem(size => 8); } +PMULHUW SSE 00001111 11100100 !emit { modrm(); mem(size => 8); } +PSADBW SSE 00001111 11110110 !emit { modrm(); mem(size => 8); } +PSHUFW SSE 00001111 01110000 !emit { modrm(); mem(size => 8); imm(size => 1); } + +# SSE Cacheability Control, Prefetch, and Instruction Ordering Instructions +MASKMOVQ SSE 00001111 11110111 !emit { modrm(mod => MOD_DIRECT); mem(size => 8, base => REG_EDI); } +MOVNTQ SSE 00001111 11100111 !emit { modrm(mod => ~MOD_DIRECT); mem(size => 8); } +MOVNTPS SSE 00001111 00101011 !emit { modrm(mod => ~MOD_DIRECT); mem(size => 16, align => 16); } +PREFETCHT0 SSE 00001111 00011000 !emit { modrm(mod => ~MOD_DIRECT, reg => 1); mem(size => 1); } +PREFETCHT1 SSE 00001111 00011000 !emit { modrm(mod => ~MOD_DIRECT, reg => 2); mem(size => 1); } +PREFETCHT2 SSE 00001111 00011000 !emit { modrm(mod => ~MOD_DIRECT, reg => 3); mem(size => 1); } +PREFETCHNTA SSE 00001111 00011000 !emit { modrm(mod => ~MOD_DIRECT, reg => 0); mem(size => 1); } +SFENCE SSE 00001111 10101110 !emit { modrm(mod => MOD_DIRECT, reg => 7); }