diff --git a/hw/pci-bridge/Kconfig b/hw/pci-bridge/Kconfig
index a51ec716f5..f6ff8975a5 100644
--- a/hw/pci-bridge/Kconfig
+++ b/hw/pci-bridge/Kconfig
@@ -27,3 +27,8 @@ config DEC_PCI
 
 config SIMBA
     bool
+
+config CCIX_SWITCH
+    default y if CCIX_EP
+    depends on PCI_EXPRESS && MSI_NONBROKEN
+    select CCIX_LIB
diff --git a/hw/pci-bridge/Makefile.objs b/hw/pci-bridge/Makefile.objs
index 47065f87d9..e266e39fed 100644
--- a/hw/pci-bridge/Makefile.objs
+++ b/hw/pci-bridge/Makefile.objs
@@ -8,3 +8,4 @@ common-obj-$(CONFIG_I82801B11) += i82801b11.o
 common-obj-$(CONFIG_DEC_PCI) += dec.o
 # Sun4u
 common-obj-$(CONFIG_SIMBA) += simba.o
+common-obj-$(CONFIG_CCIX_SWITCH) += ccix_upstream.o
diff --git a/hw/pci-bridge/ccix_upstream.c b/hw/pci-bridge/ccix_upstream.c
new file mode 100644
index 0000000000..f2b8441fba
--- /dev/null
+++ b/hw/pci-bridge/ccix_upstream.c
@@ -0,0 +1,197 @@
+/*
+ * ccix_upstream.c
+ * CCIX / pci express upstream port switch
+ *
+ * Copyright (c) 2019 Jonathan Camerom <Jonathan.Cameron@huawei.com>
+ *                    Huawei
+ * Based on: xio3130_downstream.c
+ * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
+ *                    VA Linux Systems Japan K.K.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/pci/pci_ids.h"
+#include "hw/pci/msi.h"
+#include "hw/pci/pcie.h"
+#include "hw/pci/pcie_port.h"
+#include "hw/misc/ccix.h"
+#include "qemu/module.h"
+
+/*
+ * As no CCIX devices have publically available specs, just use
+ * the xio3130 elements for the PCIe specific parts.
+ */
+#define XIO3130_REVISION                0x2
+#define XIO3130_MSI_OFFSET              0x70
+#define XIO3130_MSI_SUPPORTED_FLAGS     PCI_MSI_FLAGS_64BIT
+#define XIO3130_MSI_NR_VECTOR           1
+#define XIO3130_SSVID_OFFSET            0x80
+#define XIO3130_SSVID_SVID              0
+#define XIO3130_SSVID_SSID              0
+#define XIO3130_EXP_OFFSET              0x90
+#define XIO3130_AER_OFFSET              0x100
+
+#define TYPE_CCIX_UP_PORT "ccix-upstream-port"
+
+#define CCIX_UP_DEV(obj) OBJECT_CHECK(CCIXUpPortState, (obj), TYPE_CCIX_UP_PORT)
+
+typedef struct CCIXUpPortState {
+    PCIEPort parent_obj;
+    struct CCIXState s;
+} CCIXUpPortState;
+
+static void ccix_upstream_port_write_config(PCIDevice *d, uint32_t address,
+                                            uint32_t val, int len)
+{
+    CCIXUpPortState *s = CCIX_UP_DEV(d);
+    pci_bridge_write_config(d, address, val, len);
+    pcie_cap_flr_write_config(d, address, val, len);
+    pcie_aer_write_config(d, address, val, len);
+    ccix_write_config(d, &s->s, address, val, len);
+}
+
+static void xio3130_upstream_reset(DeviceState *qdev)
+{
+    PCIDevice *d = PCI_DEVICE(qdev);
+
+    pci_bridge_reset(qdev);
+    pcie_cap_deverr_reset(d);
+}
+
+static void ccix_upstream_port_realize(PCIDevice *d, Error **errp)
+{
+    CCIXUpPortState *s = CCIX_UP_DEV(d);
+    PCIEPort *p = PCIE_PORT(d);
+    uint32_t offset = 0x180;
+    int rc;
+
+    pci_bridge_initfn(d, TYPE_PCIE_BUS);
+    pcie_port_init_reg(d);
+
+    rc = msi_init(d, XIO3130_MSI_OFFSET, XIO3130_MSI_NR_VECTOR,
+                  XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64BIT,
+                  XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT,
+                  errp);
+    if (rc < 0) {
+        assert(rc == -ENOTSUP);
+        goto err_bridge;
+    }
+
+    rc = pci_bridge_ssvid_init(d, XIO3130_SSVID_OFFSET,
+                               XIO3130_SSVID_SVID, XIO3130_SSVID_SSID,
+                               errp);
+    if (rc < 0) {
+        goto err_bridge;
+    }
+
+    rc = pcie_cap_init(d, XIO3130_EXP_OFFSET, PCI_EXP_TYPE_UPSTREAM,
+                       p->port, errp);
+    if (rc < 0) {
+        goto err_msi;
+    }
+    pcie_cap_flr_init(d);
+    pcie_cap_deverr_init(d);
+
+    rc = pcie_aer_init(d, PCI_ERR_VER, XIO3130_AER_OFFSET,
+                       PCI_ERR_SIZEOF, errp);
+    if (rc < 0) {
+        goto err;
+    }
+    initialize_ccixstate(&s->s, d);
+    ccix_set_port(&s->s);
+    offset = ccix_add_prldvsec(d, &s->s, offset);
+    ccix_register(&s->s);
+
+    return;
+
+err:
+    pcie_cap_exit(d);
+err_msi:
+    msi_uninit(d);
+err_bridge:
+    pci_bridge_exitfn(d);
+}
+
+static Property ccix_props[] = {
+    DEFINE_PROP_STRING("ccix_device", CCIXUpPortState, s.ccix_dev_name),
+    DEFINE_PROP_BIT("primaryport", CCIXUpPortState, s.flags, PRIMARY_PORT_BIT, true),
+    DEFINE_PROP_UINT8("port_id", CCIXUpPortState, s.port_id, 0),
+    DEFINE_PROP_UINT8("num_links", CCIXUpPortState, s.num_links, 1),
+    DEFINE_PROP_UINT8("psam_entries", CCIXUpPortState, s.psam_entries, 0),
+    DEFINE_PROP_UINT8("request_agents", CCIXUpPortState, s.num_ras, 0),
+    DEFINE_PROP_UINT8("home_agents", CCIXUpPortState, s.num_has, 0),
+    DEFINE_PROP_UINT8("hsam_entries", CCIXUpPortState, s.hsam_entries, 0),
+    DEFINE_PROP_UINT8("rsam_entries", CCIXUpPortState, s.rsam_entries, 0),
+    DEFINE_PROP_END_OF_LIST(),
+};
+
+static void ccix_upstream_exitfn(PCIDevice *d)
+{
+    pcie_aer_exit(d);
+    pcie_cap_exit(d);
+    msi_uninit(d);
+    pci_bridge_exitfn(d);
+}
+
+static const VMStateDescription vmstate_ccix_upstream = {
+    .name = "ccix-upstream-port",
+    .priority = MIG_PRI_PCI_BUS,
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .fields = (VMStateField[]) {
+        VMSTATE_PCI_DEVICE(parent_obj.parent_obj, PCIEPort),
+        VMSTATE_STRUCT(parent_obj.parent_obj.exp.aer_log, PCIEPort, 0,
+                       vmstate_pcie_aer_log, PCIEAERLog),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
+static void ccix_upstream_port_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
+
+    k->is_bridge = true;
+    k->config_write = ccix_upstream_port_write_config;
+    k->realize = ccix_upstream_port_realize;
+    k->exit = ccix_upstream_exitfn;
+    k->vendor_id = PCI_VENDOR_ID_HUAWEI;
+    k->device_id = PCI_DEVICE_ID_HUAWEI_CCIX_UP;
+    k->revision = 1;
+    set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
+    dc->desc = "CCIX / PCIe switch upstream port";
+    dc->props = ccix_props;
+    dc->reset = xio3130_upstream_reset;
+    dc->vmsd = &vmstate_ccix_upstream;
+}
+
+static const TypeInfo ccix_upstream_port_info = {
+    .name = TYPE_CCIX_UP_PORT,
+    .parent = TYPE_PCIE_PORT,
+    .class_init = ccix_upstream_port_init,
+    .instance_size = sizeof(CCIXUpPortState),
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_PCIE_DEVICE },
+        { }
+    },
+};
+
+static void ccix_upstream_register_types(void)
+{
+    type_register_static(&ccix_upstream_port_info);
+}
+
+type_init(ccix_upstream_register_types)
