From patchwork Thu Jun 27 05:27:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Rolnik X-Patchwork-Id: 11018811 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id F11021575 for ; Thu, 27 Jun 2019 05:29:24 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E2F1528A19 for ; Thu, 27 Jun 2019 05:29:24 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D64A728A1B; Thu, 27 Jun 2019 05:29:24 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.0 required=2.0 tests=BAYES_00,DKIM_ADSP_CUSTOM_MED, DKIM_INVALID,DKIM_SIGNED,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 5787928A19 for ; Thu, 27 Jun 2019 05:29:24 +0000 (UTC) Received: from localhost ([::1]:46450 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hgMyJ-0007U0-Ko for patchwork-qemu-devel@patchwork.kernel.org; Thu, 27 Jun 2019 01:29:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58875) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hgMx5-0005vV-8u for qemu-devel@nongnu.org; Thu, 27 Jun 2019 01:28:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hgMx3-0004YQ-Vv for qemu-devel@nongnu.org; Thu, 27 Jun 2019 01:28:07 -0400 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]:50646) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hgMx0-0004Sy-DB for qemu-devel@nongnu.org; Thu, 27 Jun 2019 01:28:03 -0400 Received: by mail-wm1-x343.google.com with SMTP id c66so4325483wmf.0 for ; Wed, 26 Jun 2019 22:28:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=4ZFZMsmQe254in4ul0D3ojbiZelqUBf277QY25Y6XAA=; b=Kq6pQmoxPiuNZCWZ6ERXB1u1u+jzq6Y/J25vbnmUuV5yq5/w3F7H2NvuTpP9tUaiiX 5Za0H+HXlQ1Unra4QWh/XeSWkM6V/hFwZ+b5P85BcMT20lB9B0VU0i/B4AxN0xj2+C7M uXhXtu6Ei+NDJrGIRHH6tCaz5bHwvNsfY+Qecrz7uOweIjV6kcwPuTJDdb86J5tHCKoI 8o+CS6S5LHaECFZnHAvpbTQANTVEpJu/+/Yv5qk/XfqGjaa/h1HkrffGW2vi5+k1aw6s uaic5O/a0WtYe503cWwNUzncwkzUQ13+Fg16Uu5g6FRDylsr6L8DPoSlCl4nDyA/UAH6 AEBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=4ZFZMsmQe254in4ul0D3ojbiZelqUBf277QY25Y6XAA=; b=P+HPmB4kJjY1MATgQI437f6Wc89aaaty1rGrJs1dPUYGgJqKikxBFiE7SPIYEol1XM ZD9glzfxsD/NIyIQ6H9eFYB1sFEMmn/bCVB/52vefQKnK26DpgVFgKbfliH1CZKXc5cs nJVOOrMnZsSt6wwa+oOvyUO9rTeGEPfCfTVlIVTyjzDidywiIYX7dI6eXNam6/pXFR/N 5AFZGsOq1ZCk6UevuUr1X78mATGRDVpp+aYa7fPstLytvOTTYgJXy5HHuOp7ypRE9fbn g4Ek2Ws5FgUnKhedB+Vu6Qp5X5rD6oX/fvLJcDawnLnXJg/DQV7sBYKqOv05r8whFom1 7Jfw== X-Gm-Message-State: APjAAAWOWwswRtPMzdsyzi6FtN14joAyiqQbeQFWDjKyn0O25GGfUVnh sl9bWymn+YMKfEz24Mu+qlHZ9veG0FYCLA== X-Google-Smtp-Source: APXvYqxMizo35ZBxqUQkqyXXPl/Wf1hOFwtDII8KWJNKJVYjpfexl/8iEcqdCmGd4lAB3hOwqDLstw== X-Received: by 2002:a05:600c:2189:: with SMTP id e9mr1558946wme.56.1561613280355; Wed, 26 Jun 2019 22:28:00 -0700 (PDT) Received: from localhost.localdomain (bzq-79-182-104-87.red.bezeqint.net. [79.182.104.87]) by smtp.gmail.com with ESMTPSA id v18sm916389wrd.51.2019.06.26.22.27.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 26 Jun 2019 22:27:59 -0700 (PDT) From: Michael Rolnik To: qemu-devel@nongnu.org Date: Thu, 27 Jun 2019 08:27:46 +0300 Message-Id: <20190627052750.31856-4-mrolnik@gmail.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190627052750.31856-1-mrolnik@gmail.com> References: <20190627052750.31856-1-mrolnik@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 Subject: [Qemu-devel] [PATCH v23 3/7] target/avr: Add instruction decoding X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Rolnik , richard.henderson@linaro.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP This includes: - encoding of all 16 bit instructions - encoding of all 32 bit instructions Signed-off-by: Michael Rolnik --- target/avr/insn.decode | 175 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 175 insertions(+) create mode 100644 target/avr/insn.decode diff --git a/target/avr/insn.decode b/target/avr/insn.decode new file mode 100644 index 0000000000..6b387762c6 --- /dev/null +++ b/target/avr/insn.decode @@ -0,0 +1,175 @@ +# +# A = [16 .. 31] +# B = [16 .. 23] +# C = [24, 26, 28, 30] +# D = [0, 2, 4, 6, 8, .. 30] + +%rd 4:5 +%rr 9:1 0:4 + +&rd_rr rd rr +&rd_imm rd imm + +@op_rd_rr .... .. . ..... .... &rd_rr rd=%rd rr=%rr +ADD 0000 11 . ..... .... @op_rd_rr +ADC 0001 11 . ..... .... @op_rd_rr +AND 0010 00 . ..... .... @op_rd_rr +CP 0001 01 . ..... .... @op_rd_rr +CPC 0000 01 . ..... .... @op_rd_rr +CPSE 0001 00 . ..... .... @op_rd_rr +EOR 0010 01 . ..... .... @op_rd_rr +MOV 0010 11 . ..... .... @op_rd_rr +MUL 1001 11 . ..... .... @op_rd_rr +OR 0010 10 . ..... .... @op_rd_rr +SBC 0000 10 . ..... .... @op_rd_rr +SUB 0001 10 . ..... .... @op_rd_rr + + +%rd_c 4:2 !function=to_C +%imm6 6:2 0:4 + +@op_rd_imm6 .... .... .. .. .... &rd_imm rd=%rd_c imm=%imm6 +ADIW 1001 0110 .. .. .... @op_rd_imm6 +SBIW 1001 0111 .. .. .... @op_rd_imm6 + + +%rd_a 4:4 !function=to_A +%rr_a 0:4 !function=to_A +%rd_d 4:4 !function=to_D +%rr_d 0:4 !function=to_D +%imm8 8:4 0:4 + +@op_rd_imm8 .... .... .... .... &rd_imm rd=%rd_a imm=%imm8 +ANDI 0111 .... .... .... @op_rd_imm8 +CPI 0011 .... .... .... @op_rd_imm8 +LDI 1110 .... .... .... @op_rd_imm8 +ORI 0110 .... .... .... @op_rd_imm8 +SBCI 0100 .... .... .... @op_rd_imm8 +SUBI 0101 .... .... .... @op_rd_imm8 + + +@op_rd .... ... rd:5 .... +ASR 1001 010 ..... 0101 @op_rd +COM 1001 010 ..... 0000 @op_rd +DEC 1001 010 ..... 1010 @op_rd +ELPM2 1001 000 ..... 0110 @op_rd +ELPMX 1001 000 ..... 0111 @op_rd +INC 1001 010 ..... 0011 @op_rd +LDX1 1001 000 ..... 1100 @op_rd +LDX2 1001 000 ..... 1101 @op_rd +LDX3 1001 000 ..... 1110 @op_rd +LDY2 1001 000 ..... 1001 @op_rd +LDY3 1001 000 ..... 1010 @op_rd +LDZ2 1001 000 ..... 0001 @op_rd +LDZ3 1001 000 ..... 0010 @op_rd +LPM2 1001 000 ..... 0100 @op_rd +LPMX 1001 000 ..... 0101 @op_rd +LSR 1001 010 ..... 0110 @op_rd +NEG 1001 010 ..... 0001 @op_rd +POP 1001 000 ..... 1111 @op_rd +PUSH 1001 001 ..... 1111 @op_rd +ROR 1001 010 ..... 0111 @op_rd +STY2 1001 001 ..... 1001 @op_rd +STY3 1001 001 ..... 1010 @op_rd +STZ2 1001 001 ..... 0001 @op_rd +STZ3 1001 001 ..... 0010 @op_rd +SWAP 1001 010 ..... 0010 @op_rd + + +@op_bit .... .... . bit:3 .... +BCLR 1001 0100 1 ... 1000 @op_bit +BSET 1001 0100 0 ... 1000 @op_bit + + +@op_rd_bit .... ... rd:5 . bit:3 +BLD 1111 100 ..... 0 ... @op_rd_bit +BST 1111 101 ..... 0 ... @op_rd_bit + + +@op_bit_imm .... .. imm:s7 bit:3 +BRBC 1111 01 ....... ... @op_bit_imm +BRBS 1111 00 ....... ... @op_bit_imm + + +BREAK 1001 0101 1001 1000 +EICALL 1001 0101 0001 1001 +EIJMP 1001 0100 0001 1001 +ELPM1 1001 0101 1101 1000 +ICALL 1001 0101 0000 1001 +IJMP 1001 0100 0000 1001 +LPM1 1001 0101 1100 1000 +NOP 0000 0000 0000 0000 +RET 1001 0101 0000 1000 +RETI 1001 0101 0001 1000 +SLEEP 1001 0101 1000 1000 +SPM 1001 0101 1110 1000 +SPMX 1001 0101 1111 1000 +WDR 1001 0101 1010 1000 + + +@op_reg_bit .... .... reg:5 bit:3 +CBI 1001 1000 ..... ... @op_reg_bit +SBI 1001 1010 ..... ... @op_reg_bit +SBIC 1001 1001 ..... ... @op_reg_bit +SBIS 1001 1011 ..... ... @op_reg_bit + + +DES 1001 0100 imm:4 1011 + + +%rd_b 4:3 !function=to_B +%rr_b 0:3 !function=to_B +@fmul .... .... . ... . ... &rd_rr rd=%rd_b rr=%rr_b +FMUL 0000 0011 0 ... 1 ... @fmul +FMULS 0000 0011 1 ... 0 ... @fmul +FMULSU 0000 0011 1 ... 1 ... @fmul +MULSU 0000 0011 0 ... 0 ... @fmul + + +%io_imm 9:2 0:4 +@io_rd_imm .... . .. ..... .... &rd_imm rd=%rd imm=%io_imm +IN 1011 0 .. ..... .... @io_rd_imm +OUT 1011 1 .. ..... .... @io_rd_imm + + +XCH 1001 001 rd:5 0100 +LAC 1001 001 rd:5 0110 +LAS 1001 001 rd:5 0101 +LAT 1001 001 rd:5 0111 +STX1 1001 001 rr:5 1100 +STX2 1001 001 rr:5 1101 +STX3 1001 001 rr:5 1110 + + +%ldst_d_imm 13:1 10:2 0:3 +@ldst_d .. . . .. . rd:5 . ... &rd_imm imm=%ldst_d_imm +LDDY 10 . 0 .. 0 ..... 1 ... @ldst_d +LDDZ 10 . 0 .. 0 ..... 0 ... @ldst_d +STDY 10 . 0 .. 1 ..... 1 ... @ldst_d +STDZ 10 . 0 .. 1 ..... 0 ... @ldst_d + + +MOVW 0000 0001 .... .... &rd_rr rd=%rd_d rr=%rr_d +MULS 0000 0010 .... .... &rd_rr rd=%rd_a rr=%rr_a + +RCALL 1101 imm:s12 +RJMP 1100 imm:s12 + +SBRC 1111 110 rr:5 0 bit:3 +SBRS 1111 111 rr:5 0 bit:3 + +# The 22-bit immediate is partially in the opcode word, +# and partially in the next. Use append_16 to build the +# complete 22-bit value. +%imm_call 4:5 0:1 !function=append_16 +CALL 1001 010 ..... 111 . imm=%imm_call +JMP 1001 010 ..... 110 . imm=%imm_call + + +# The 16-bit immediate is completely in the next word. +# Fields cannot be defined with no bits, so we cannot play +# the same trick and append to a zero-bit value. +# Defer reading the immediate until trans_{LDS,STS}. +@ldst_s .... ... rd:5 .... imm=0 +LDS 1001 000 ..... 0000 @ldst_s +STS 1001 001 ..... 0000 @ldst_s