| Message ID | 20190630204601.30574-5-clg@kaod.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | ppc/pnv: add XIVE support for KVM guests | expand |
On Sun, Jun 30, 2019 at 10:45:55PM +0200, Cédric Le Goater wrote: > When a CPU is reseted, the hypervisor (Linux or OPAL) invalidates the > POOL interrupt context of a CPU with this special command. It returns > the POOL CAM line value and resets the VP bit. > > Fixes: 4836b45510aa ("ppc/xive: activate HV support") > Signed-off-by: Cédric Le Goater <clg@kaod.org> Applied to ppc-for-4.1. > --- > hw/intc/xive.c | 19 ++++++++++--------- > 1 file changed, 10 insertions(+), 9 deletions(-) > > diff --git a/hw/intc/xive.c b/hw/intc/xive.c > index 534f56f86bd5..cf77bdb7d34a 100644 > --- a/hw/intc/xive.c > +++ b/hw/intc/xive.c > @@ -132,6 +132,11 @@ static void xive_tctx_set_cppr(XiveTCTX *tctx, uint8_t ring, uint8_t cppr) > xive_tctx_notify(tctx, ring); > } > > +static inline uint32_t xive_tctx_word2(uint8_t *ring) > +{ > + return *((uint32_t *) &ring[TM_WORD2]); > +} > + > /* > * XIVE Thread Interrupt Management Area (TIMA) > */ > @@ -150,11 +155,12 @@ static uint64_t xive_tm_ack_hv_reg(XiveTCTX *tctx, hwaddr offset, unsigned size) > static uint64_t xive_tm_pull_pool_ctx(XiveTCTX *tctx, hwaddr offset, > unsigned size) > { > - uint64_t ret; > + uint32_t qw2w2_prev = xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]); > + uint32_t qw2w2; > > - ret = tctx->regs[TM_QW2_HV_POOL + TM_WORD2] & TM_QW2W2_POOL_CAM; > - tctx->regs[TM_QW2_HV_POOL + TM_WORD2] &= ~TM_QW2W2_POOL_CAM; > - return ret; > + qw2w2 = xive_set_field32(TM_QW2W2_VP, qw2w2_prev, 0); > + memcpy(&tctx->regs[TM_QW2_HV_POOL + TM_WORD2], &qw2w2, 4); > + return qw2w2; > } > > static void xive_tm_vt_push(XiveTCTX *tctx, hwaddr offset, > @@ -484,11 +490,6 @@ const MemoryRegionOps xive_tm_ops = { > }, > }; > > -static inline uint32_t xive_tctx_word2(uint8_t *ring) > -{ > - return *((uint32_t *) &ring[TM_WORD2]); > -} > - > static char *xive_tctx_ring_print(uint8_t *ring) > { > uint32_t w2 = xive_tctx_word2(ring);
diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 534f56f86bd5..cf77bdb7d34a 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -132,6 +132,11 @@ static void xive_tctx_set_cppr(XiveTCTX *tctx, uint8_t ring, uint8_t cppr) xive_tctx_notify(tctx, ring); } +static inline uint32_t xive_tctx_word2(uint8_t *ring) +{ + return *((uint32_t *) &ring[TM_WORD2]); +} + /* * XIVE Thread Interrupt Management Area (TIMA) */ @@ -150,11 +155,12 @@ static uint64_t xive_tm_ack_hv_reg(XiveTCTX *tctx, hwaddr offset, unsigned size) static uint64_t xive_tm_pull_pool_ctx(XiveTCTX *tctx, hwaddr offset, unsigned size) { - uint64_t ret; + uint32_t qw2w2_prev = xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]); + uint32_t qw2w2; - ret = tctx->regs[TM_QW2_HV_POOL + TM_WORD2] & TM_QW2W2_POOL_CAM; - tctx->regs[TM_QW2_HV_POOL + TM_WORD2] &= ~TM_QW2W2_POOL_CAM; - return ret; + qw2w2 = xive_set_field32(TM_QW2W2_VP, qw2w2_prev, 0); + memcpy(&tctx->regs[TM_QW2_HV_POOL + TM_WORD2], &qw2w2, 4); + return qw2w2; } static void xive_tm_vt_push(XiveTCTX *tctx, hwaddr offset, @@ -484,11 +490,6 @@ const MemoryRegionOps xive_tm_ops = { }, }; -static inline uint32_t xive_tctx_word2(uint8_t *ring) -{ - return *((uint32_t *) &ring[TM_WORD2]); -} - static char *xive_tctx_ring_print(uint8_t *ring) { uint32_t w2 = xive_tctx_word2(ring);
When a CPU is reseted, the hypervisor (Linux or OPAL) invalidates the POOL interrupt context of a CPU with this special command. It returns the POOL CAM line value and resets the VP bit. Fixes: 4836b45510aa ("ppc/xive: activate HV support") Signed-off-by: Cédric Le Goater <clg@kaod.org> --- hw/intc/xive.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-)