From patchwork Tue Jul 2 00:13:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11027101 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1D713138B for ; Tue, 2 Jul 2019 03:14:05 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 04A7728820 for ; Tue, 2 Jul 2019 03:14:05 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id EC1EC28852; Tue, 2 Jul 2019 03:14:04 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 8365E28820 for ; Tue, 2 Jul 2019 03:14:04 +0000 (UTC) Received: from localhost ([::1]:47852 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hi9F5-0004E8-U4 for patchwork-qemu-devel@patchwork.kernel.org; Mon, 01 Jul 2019 23:14:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58550) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hi6v4-0007Ya-KI for qemu-devel@nongnu.org; Mon, 01 Jul 2019 20:45:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hi6VJ-0008JI-Fy for qemu-devel@nongnu.org; Mon, 01 Jul 2019 20:18:41 -0400 Received: from mx1.redhat.com ([209.132.183.28]:53582) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hi6TL-0007ZO-7s; Mon, 01 Jul 2019 20:16:41 -0400 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.phx2.redhat.com [10.5.11.22]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 39F236EB96; Tue, 2 Jul 2019 00:16:32 +0000 (UTC) Received: from x1w.redhat.com (ovpn-204-21.brq.redhat.com [10.40.204.21]) by smtp.corp.redhat.com (Postfix) with ESMTPS id DC2361001B32; Tue, 2 Jul 2019 00:16:10 +0000 (UTC) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Date: Tue, 2 Jul 2019 02:13:01 +0200 Message-Id: <20190702001301.4768-10-philmd@redhat.com> In-Reply-To: <20190702001301.4768-1-philmd@redhat.com> References: <20190702001301.4768-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.25]); Tue, 02 Jul 2019 00:16:32 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH v2 9/9] hw/block/pflash_cfi01: Hold the PRI table offset in a variable X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , "Michael S. Tsirkin" , Max Filippov , Gerd Hoffmann , "Edgar E. Iglesias" , qemu-block@nongnu.org, Aleksandar Rikalo , =?utf-8?q?Alex_Benn=C3=A9e?= , Markus Armbruster , Laszlo Ersek , David Gibson , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Eduardo Habkost , qemu-arm@nongnu.org, Alistair Francis , John Snow , Richard Henderson , Kevin Wolf , Max Reitz , Michael Walle , qemu-ppc@nongnu.org, Wei Yang , Aleksandar Markovic , Paolo Bonzini , Aurelien Jarno Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Manufacturers are allowed to move the PRI table, this is why the offset is queryable via fixed offsets 0x15/0x16. Add a variable to hold the offset, so it will be easier to later move the PRI table. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis --- hw/block/pflash_cfi01.c | 41 ++++++++++++++++++++++++++--------------- 1 file changed, 26 insertions(+), 15 deletions(-) diff --git a/hw/block/pflash_cfi01.c b/hw/block/pflash_cfi01.c index e891112b67..f65840eb2b 100644 --- a/hw/block/pflash_cfi01.c +++ b/hw/block/pflash_cfi01.c @@ -762,6 +762,7 @@ static void pflash_cfi01_realize(DeviceState *dev, Error **errp) } /* Hardcoded CFI table */ + const uint16_t pri_ofs = 0x31; /* Standard "QRY" string */ pfl->cfi_table[0x10] = 'Q'; pfl->cfi_table[0x11] = 'R'; @@ -770,14 +771,17 @@ static void pflash_cfi01_realize(DeviceState *dev, Error **errp) pfl->cfi_table[0x13] = 0x01; pfl->cfi_table[0x14] = 0x00; /* Primary extended table address (none) */ - pfl->cfi_table[0x15] = 0x31; - pfl->cfi_table[0x16] = 0x00; + pfl->cfi_table[0x15] = pri_ofs; + pfl->cfi_table[0x16] = pri_ofs >> 8; /* Alternate command set (none) */ pfl->cfi_table[0x17] = 0x00; pfl->cfi_table[0x18] = 0x00; /* Alternate extended table (none) */ pfl->cfi_table[0x19] = 0x00; pfl->cfi_table[0x1A] = 0x00; + + /* CFI: System Interface Information */ + /* Vcc min */ pfl->cfi_table[0x1B] = 0x45; /* Vcc max */ @@ -802,6 +806,9 @@ static void pflash_cfi01_realize(DeviceState *dev, Error **errp) pfl->cfi_table[0x25] = 0x04; /* Max timeout for chip erase */ pfl->cfi_table[0x26] = 0x00; + + /* CFI: Device Geometry Definition */ + /* Device size */ pfl->cfi_table[0x27] = ctz32(device_len); /* + 1; */ /* Flash device interface (8 & 16 bits) */ @@ -826,26 +833,30 @@ static void pflash_cfi01_realize(DeviceState *dev, Error **errp) pfl->cfi_table[0x2E] = (blocks_per_device - 1) >> 8; pfl->cfi_table[0x2F] = sector_len_per_device >> 8; pfl->cfi_table[0x30] = sector_len_per_device >> 16; + assert(0x30 < pri_ofs); + + /* CFI: Primary-Vendor Specific */ /* Extended */ - pfl->cfi_table[0x31] = 'P'; - pfl->cfi_table[0x32] = 'R'; - pfl->cfi_table[0x33] = 'I'; + pfl->cfi_table[0x00 + pri_ofs] = 'P'; + pfl->cfi_table[0x01 + pri_ofs] = 'R'; + pfl->cfi_table[0x02 + pri_ofs] = 'I'; - pfl->cfi_table[0x34] = '1'; - pfl->cfi_table[0x35] = '0'; + pfl->cfi_table[0x03 + pri_ofs] = '1'; + pfl->cfi_table[0x04 + pri_ofs] = '0'; - pfl->cfi_table[0x36] = 0x00; - pfl->cfi_table[0x37] = 0x00; - pfl->cfi_table[0x38] = 0x00; - pfl->cfi_table[0x39] = 0x00; + pfl->cfi_table[0x05 + pri_ofs] = 0x00; /* Optional features */ + pfl->cfi_table[0x06 + pri_ofs] = 0x00; + pfl->cfi_table[0x07 + pri_ofs] = 0x00; + pfl->cfi_table[0x08 + pri_ofs] = 0x00; - pfl->cfi_table[0x3a] = 0x00; + pfl->cfi_table[0x09 + pri_ofs] = 0x00; /* Func. supported after suspend */ - pfl->cfi_table[0x3b] = 0x00; - pfl->cfi_table[0x3c] = 0x00; + pfl->cfi_table[0x0a + pri_ofs] = 0x00; /* Block status register mask */ + pfl->cfi_table[0x0b + pri_ofs] = 0x00; - pfl->cfi_table[0x3f] = 0x01; /* Number of protection fields */ + pfl->cfi_table[0x0e + pri_ofs] = 0x01; /* Number of protection fields */ + assert(0x0e + pri_ofs < ARRAY_SIZE(pfl->cfi_table)); } static void pflash_cfi01_system_reset(DeviceState *dev)