| Message ID | 20190702001301.4768-5-philmd@redhat.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | hw/block/pflash_cfi01: Add DeviceReset() handler | expand |
On 7/1/19 8:12 PM, Philippe Mathieu-Daudé wrote: > When the state machine is ready to accept command, the bit 7 of > the status register (SR) is set to 1. > The guest polls the status register and check this bit before > writting command to the internal 'Write State Machine' (WSM). writing > > Set SR.7 bit to 1 when the device is created. > Right, ok -- it looks like we don't set this on realize otherwise. (Or if we do, it's not obvious where or how.) > Reference: Read Array Flowchart > "Common Flash Interface (CFI) and Command Sets" > (Intel Application Note 646) > Appendix B "Basic Command Set" > > Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: John Snow <jsnow@redhat.com> > --- > hw/block/pflash_cfi01.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/hw/block/pflash_cfi01.c b/hw/block/pflash_cfi01.c > index 33c77f6569..dd1dfd266b 100644 > --- a/hw/block/pflash_cfi01.c > +++ b/hw/block/pflash_cfi01.c > @@ -764,7 +764,7 @@ static void pflash_cfi01_realize(DeviceState *dev, Error **errp) > } > > pflash_mode_read_array(pfl); > - pfl->status = 0; > + pfl->status = 0x80; /* WSM ready */ > /* Hardcoded CFI table */ > /* Standard "QRY" string */ > pfl->cfi_table[0x10] = 'Q'; >
On Mon, Jul 1, 2019 at 5:14 PM Philippe Mathieu-Daudé <philmd@redhat.com> wrote: > > When the state machine is ready to accept command, the bit 7 of > the status register (SR) is set to 1. > The guest polls the status register and check this bit before > writting command to the internal 'Write State Machine' (WSM). > > Set SR.7 bit to 1 when the device is created. > > Reference: Read Array Flowchart > "Common Flash Interface (CFI) and Command Sets" > (Intel Application Note 646) > Appendix B "Basic Command Set" > > Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > hw/block/pflash_cfi01.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/hw/block/pflash_cfi01.c b/hw/block/pflash_cfi01.c > index 33c77f6569..dd1dfd266b 100644 > --- a/hw/block/pflash_cfi01.c > +++ b/hw/block/pflash_cfi01.c > @@ -764,7 +764,7 @@ static void pflash_cfi01_realize(DeviceState *dev, Error **errp) > } > > pflash_mode_read_array(pfl); > - pfl->status = 0; > + pfl->status = 0x80; /* WSM ready */ > /* Hardcoded CFI table */ > /* Standard "QRY" string */ > pfl->cfi_table[0x10] = 'Q'; > -- > 2.20.1 >
diff --git a/hw/block/pflash_cfi01.c b/hw/block/pflash_cfi01.c index 33c77f6569..dd1dfd266b 100644 --- a/hw/block/pflash_cfi01.c +++ b/hw/block/pflash_cfi01.c @@ -764,7 +764,7 @@ static void pflash_cfi01_realize(DeviceState *dev, Error **errp) } pflash_mode_read_array(pfl); - pfl->status = 0; + pfl->status = 0x80; /* WSM ready */ /* Hardcoded CFI table */ /* Standard "QRY" string */ pfl->cfi_table[0x10] = 'Q';
When the state machine is ready to accept command, the bit 7 of the status register (SR) is set to 1. The guest polls the status register and check this bit before writting command to the internal 'Write State Machine' (WSM). Set SR.7 bit to 1 when the device is created. Reference: Read Array Flowchart "Common Flash Interface (CFI) and Command Sets" (Intel Application Note 646) Appendix B "Basic Command Set" Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> --- hw/block/pflash_cfi01.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)