From patchwork Tue Jul 16 14:51:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tao Xu X-Patchwork-Id: 11046221 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6B666112C for ; Tue, 16 Jul 2019 14:57:07 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 59E0C27F94 for ; Tue, 16 Jul 2019 14:57:07 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4D96C28585; Tue, 16 Jul 2019 14:57:07 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 751F0285EC for ; Tue, 16 Jul 2019 14:57:06 +0000 (UTC) Received: from localhost ([::1]:49812 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hnOt7-0007N1-Bq for patchwork-qemu-devel@patchwork.kernel.org; Tue, 16 Jul 2019 10:57:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49868) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hnOqi-0005WD-GP for qemu-devel@nongnu.org; Tue, 16 Jul 2019 10:54:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hnOqg-000189-Cy for qemu-devel@nongnu.org; Tue, 16 Jul 2019 10:54:36 -0400 Received: from mga03.intel.com ([134.134.136.65]:20995) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hnOqg-0000za-1V for qemu-devel@nongnu.org; Tue, 16 Jul 2019 10:54:34 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Jul 2019 07:54:33 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.63,498,1557212400"; d="scan'208";a="319014819" Received: from tao-optiplex-7060.sh.intel.com ([10.239.13.104]) by orsmga004.jf.intel.com with ESMTP; 16 Jul 2019 07:54:31 -0700 From: Tao Xu To: imammedo@redhat.com, eblake@redhat.com, ehabkost@redhat.com Date: Tue, 16 Jul 2019 22:51:20 +0800 Message-Id: <20190716145121.19578-11-tao3.xu@intel.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190716145121.19578-1-tao3.xu@intel.com> References: <20190716145121.19578-1-tao3.xu@intel.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 134.134.136.65 Subject: [Qemu-devel] [PATCH v7 10/11] numa: Extend the CLI to provide memory side cache information X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jingqi.liu@intel.com, tao3.xu@intel.com, fan.du@intel.com, qemu-devel@nongnu.org, jonathan.cameron@huawei.com, dan.j.williams@intel.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Liu Jingqi Add -numa hmat-cache option to provide Memory Side Cache Information. These memory attributes help to build Memory Side Cache Information Structure(s) in ACPI Heterogeneous Memory Attribute Table (HMAT). Signed-off-by: Liu Jingqi Signed-off-by: Tao Xu --- No changes in v7. Changes in v6: - Add add reference to ACPI 6.3 spec (Igor) - Update the designator to 4.2 (Eric) --- hw/core/numa.c | 67 +++++++++++++++++++++++++++++++++++ include/sysemu/numa.h | 2 ++ qapi/machine.json | 81 +++++++++++++++++++++++++++++++++++++++++-- qemu-options.hx | 14 +++++++- 4 files changed, 161 insertions(+), 3 deletions(-) diff --git a/hw/core/numa.c b/hw/core/numa.c index 83ead77191..75db35ac19 100644 --- a/hw/core/numa.c +++ b/hw/core/numa.c @@ -304,6 +304,67 @@ void parse_numa_hmat_lb(MachineState *ms, NumaHmatLBOptions *node, } } +void parse_numa_hmat_cache(MachineState *ms, NumaHmatCacheOptions *node, + Error **errp) +{ + int nb_numa_nodes = ms->numa_state->num_nodes; + HMAT_Cache_Info *hmat_cache = NULL; + + if (node->node_id >= nb_numa_nodes) { + error_setg(errp, "Invalid node-id=%" PRIu32 + ", it should be less than %d.", + node->node_id, nb_numa_nodes); + return; + } + + if (node->total > MAX_HMAT_CACHE_LEVEL) { + error_setg(errp, "Invalid total=%" PRIu8 + ", it should be less than or equal to %d.", + node->total, MAX_HMAT_CACHE_LEVEL); + return; + } + if (node->level > node->total) { + error_setg(errp, "Invalid level=%" PRIu8 + ", it should be less than or equal to" + " total=%" PRIu8 ".", + node->level, node->total); + return; + } + if (ms->numa_state->hmat_cache[node->node_id][node->level]) { + error_setg(errp, "Duplicate configuration of the side cache for " + "node-id=%" PRIu32 " and level=%" PRIu8 ".", + node->node_id, node->level); + return; + } + + if ((node->level > 1) && + ms->numa_state->hmat_cache[node->node_id][node->level - 1] && + (node->size >= + ms->numa_state->hmat_cache[node->node_id][node->level - 1]->size)) { + error_setg(errp, "Invalid size=0x%" PRIx64 + ", the size of level=%" PRIu8 + " should be less than the size(0x%" PRIx64 + ") of level=%" PRIu8 ".", + node->size, node->level, + ms->numa_state->hmat_cache[node->node_id] + [node->level - 1]->size, + node->level - 1); + return; + } + + hmat_cache = g_malloc0(sizeof(*hmat_cache)); + + hmat_cache->mem_proximity = node->node_id; + hmat_cache->size = node->size; + hmat_cache->total_levels = node->total; + hmat_cache->level = node->level; + hmat_cache->associativity = node->assoc; + hmat_cache->write_policy = node->policy; + hmat_cache->line_size = node->line; + + ms->numa_state->hmat_cache[node->node_id][node->level] = hmat_cache; +} + void set_numa_options(MachineState *ms, NumaOptions *object, Error **errp) { Error *err = NULL; @@ -348,6 +409,12 @@ void set_numa_options(MachineState *ms, NumaOptions *object, Error **errp) goto end; } break; + case NUMA_OPTIONS_TYPE_HMAT_CACHE: + parse_numa_hmat_cache(ms, &object->u.hmat_cache, &err); + if (err) { + goto end; + } + break; default: abort(); } diff --git a/include/sysemu/numa.h b/include/sysemu/numa.h index f0857b7ee6..9009bbdee3 100644 --- a/include/sysemu/numa.h +++ b/include/sysemu/numa.h @@ -43,6 +43,8 @@ void set_numa_options(MachineState *ms, NumaOptions *object, Error **errp); void parse_numa_opts(MachineState *ms); void parse_numa_hmat_lb(MachineState *ms, NumaHmatLBOptions *node, Error **errp); +void parse_numa_hmat_cache(MachineState *ms, NumaHmatCacheOptions *node, + Error **errp); void numa_complete_configuration(MachineState *ms); void query_numa_node_mem(NumaNodeMem node_mem[], MachineState *ms); extern QemuOptsList qemu_numa_opts; diff --git a/qapi/machine.json b/qapi/machine.json index 25f5b0321d..65a3584b92 100644 --- a/qapi/machine.json +++ b/qapi/machine.json @@ -379,10 +379,12 @@ # # @hmat-lb: memory latency and bandwidth information (Since: 4.2) # +# @hmat-cache: memory side cache information (Since: 4.2) +# # Since: 2.1 ## { 'enum': 'NumaOptionsType', - 'data': [ 'node', 'dist', 'cpu', 'hmat-lb' ] } + 'data': [ 'node', 'dist', 'cpu', 'hmat-lb', 'hmat-cache' ] } ## # @NumaOptions: @@ -398,7 +400,8 @@ 'node': 'NumaNodeOptions', 'dist': 'NumaDistOptions', 'cpu': 'NumaCpuOptions', - 'hmat-lb': 'NumaHmatLBOptions' }} + 'hmat-lb': 'NumaHmatLBOptions', + 'hmat-cache': 'NumaHmatCacheOptions' }} ## # @NumaNodeOptions: @@ -600,6 +603,80 @@ '*latency': 'uint16', '*bandwidth': 'uint16' }} +## +# @HmatCacheAssociativity: +# +# Cache associativity in the Memory Side Cache +# Information Structure of HMAT +# +# For more information of @HmatCacheAssociativity see +# the chapter 5.2.27.5: Table 5-143 of ACPI 6.3 spec. +# +# @none: None +# +# @direct: Direct Mapped +# +# @complex: Complex Cache Indexing (implementation specific) +# +# Since: 4.2 +## +{ 'enum': 'HmatCacheAssociativity', + 'data': [ 'none', 'direct', 'complex' ] } + +## +# @HmatCacheWritePolicy: +# +# Cache write policy in the Memory Side Cache +# Information Structure of HMAT +# +# For more information of @HmatCacheWritePolicy see +# the chapter 5.2.27.5: Table 5-143: Field "Cache Attributes" of ACPI 6.3 spec. +# +# @none: None +# +# @write-back: Write Back (WB) +# +# @write-through: Write Through (WT) +# +# Since: 4.2 +## +{ 'enum': 'HmatCacheWritePolicy', + 'data': [ 'none', 'write-back', 'write-through' ] } + +## +# @NumaHmatCacheOptions: +# +# Set the memory side cache information for a given memory domain. +# +# For more information of @NumaHmatCacheOptions see +# the chapter 5.2.27.5: Table 5-143: Field "Cache Attributes" of ACPI 6.3 spec. +# +# @node-id: the memory proximity domain to which the memory belongs. +# +# @size: the size of memory side cache in bytes. +# +# @total: the total cache levels for this memory proximity domain. +# +# @level: the cache level described in this structure. +# +# @assoc: the cache associativity, none/direct-mapped/complex(complex cache indexing). +# +# @policy: the write policy, none/write-back/write-through. +# +# @line: the cache Line size in bytes. +# +# Since: 4.2 +## +{ 'struct': 'NumaHmatCacheOptions', + 'data': { + 'node-id': 'uint32', + 'size': 'size', + 'total': 'uint8', + 'level': 'uint8', + 'assoc': 'HmatCacheAssociativity', + 'policy': 'HmatCacheWritePolicy', + 'line': 'uint16' }} + ## # @HostMemPolicy: # diff --git a/qemu-options.hx b/qemu-options.hx index 609ea40086..5f3b2fd234 100644 --- a/qemu-options.hx +++ b/qemu-options.hx @@ -165,7 +165,8 @@ DEF("numa", HAS_ARG, QEMU_OPTION_numa, "-numa node[,memdev=id][,cpus=firstcpu[-lastcpu]][,nodeid=node][,initiator=node]\n" "-numa dist,src=source,dst=destination,val=distance\n" "-numa cpu,node-id=node[,socket-id=x][,core-id=y][,thread-id=z]\n" - "-numa hmat-lb,initiator=node,target=node,hierarchy=memory|first-level|second-level|third-level,data-type=access-latency|read-latency|write-latency[,base-lat=blat][,base-bw=bbw][,latency=lat][,bandwidth=bw]\n", + "-numa hmat-lb,initiator=node,target=node,hierarchy=memory|first-level|second-level|third-level,data-type=access-latency|read-latency|write-latency[,base-lat=blat][,base-bw=bbw][,latency=lat][,bandwidth=bw]\n" + "-numa hmat-cache,node-id=node,size=size,total=total,level=level[,assoc=none|direct|complex][,policy=none|write-back|write-through][,line=size]\n", QEMU_ARCH_ALL) STEXI @item -numa node[,mem=@var{size}][,cpus=@var{firstcpu}[-@var{lastcpu}]][,nodeid=@var{node}][,initiator=@var{initiator}] @@ -173,6 +174,7 @@ STEXI @itemx -numa dist,src=@var{source},dst=@var{destination},val=@var{distance} @itemx -numa cpu,node-id=@var{node}[,socket-id=@var{x}][,core-id=@var{y}][,thread-id=@var{z}] @itemx -numa hmat-lb,initiator=@var{node},target=@var{node},hierarchy=@var{str},data-type=@var{str}[,base-lat=@var{blat}][,base-bw=@var{bbw}][,latency=@var{lat}][,bandwidth=@var{bw}] +@itemx -numa hmat-cache,node-id=@var{node},size=@var{size},total=@var{total},level=@var{level}[,assoc=@var{str}][,policy=@var{str}][,line=@var{size}] @findex -numa Define a NUMA node and assign RAM and VCPUs to it. Set the NUMA distance from a source node to a destination node. @@ -275,11 +277,19 @@ Note: Due to the minimum matrix value entry value being 10, the base unit corres to a value of 10. And @var{blat} or @var{bbw} should be an integer. @var{lat} or @var{bw} is the latency/bandwidth value. +In @samp{hmat-cache} option, @var{node-id} is the NUMA-id of the memory belongs. +@var{size} is the size of memory side cache in bytes. @var{total} is the total cache levels. +@var{level} is the cache level described in this structure. @var{assoc} is the cache associativity. +"none/direct-mapped/complex(complex cache indexing). @var{policy} is the write policy. +@var{line} is the cache Line size in bytes. + For example, the following option assigns NUMA node 0 and 1. Node 0 has 2 cpus and a ram, node 1 has only a ram. The processors in node 0 access memory in node 0 with access-latency 5 picoseconds(base latency is 10), access-bandwidth 5 MB/s(base latency is 20); The processors in NUMA node 0 access memory in NUMA node 1 with access-latency 10 picoseconds(base latency is 10), access-bandwidth 10 MB/s(base latency is 20). +And for memory side cache information, NUMA node 0 and 1 both have 1 level memory +cache, size is 0x20000 bytes, policy is write-back, the cache Line size is 8 bytes: @example -m 2G \ -object memory-backend-ram,size=1024M,policy=bind,host-nodes=0,id=ram-node0 -numa node,nodeid=0,memdev=ram-node0 \ @@ -291,6 +301,8 @@ picoseconds(base latency is 10), access-bandwidth 10 MB/s(base latency is 20). -numa hmat-lb,initiator=0,target=0,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=5 \ -numa hmat-lb,initiator=0,target=1,hierarchy=memory,data-type=access-latency,base-lat=10,latency=10 \ -numa hmat-lb,initiator=0,target=1,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=10 \ +-numa hmat-cache,node-id=0,size=0x20000,total=1,level=1,assoc=direct,policy=write-back,line=8 \ +-numa hmat-cache,node-id=1,size=0x20000,total=1,level=1,assoc=direct,policy=write-back,line=8 \ @end example ETEXI