@@ -1882,8 +1882,14 @@ void pc_memory_init(PCMachineState *pcms,
exit(EXIT_FAILURE);
}
+ if (sgx_epc_above_4g(pcms->sgx_epc)) {
+ machine->device_memory->base = sgx_epc_above_4g_end(pcms->sgx_epc);
+ } else {
+ machine->device_memory->base =
+ 0x100000000ULL + pcms->above_4g_mem_size;
+ }
machine->device_memory->base =
- ROUND_UP(0x100000000ULL + pcms->above_4g_mem_size, 1 * GiB);
+ ROUND_UP(machine->device_memory->base, 1 * GiB);
if (pcmc->enforce_aligned_dimm) {
/* size device region assuming 1G page max alignment per slot */
@@ -1962,6 +1968,8 @@ uint64_t pc_pci_hole64_start(void)
if (!pcmc->broken_reserved_end) {
hole64_start += memory_region_size(&ms->device_memory->mr);
}
+ } else if (sgx_epc_above_4g(pcms->sgx_epc)) {
+ hole64_start = sgx_epc_above_4g_end(pcms->sgx_epc);
} else {
hole64_start = 0x100000000ULL + pcms->above_4g_mem_size;
}
@@ -60,4 +60,16 @@ extern int sgx_epc_enabled;
void pc_machine_init_sgx_epc(PCMachineState *pcms);
int sgx_epc_get_section(int section_nr, uint64_t *addr, uint64_t *size);
+static inline bool sgx_epc_above_4g(SGXEPCState *sgx_epc)
+{
+ return sgx_epc != NULL;
+}
+
+static inline uint64_t sgx_epc_above_4g_end(SGXEPCState *sgx_epc)
+{
+ assert(sgx_epc != NULL && sgx_epc->base >= 0x100000000ULL);
+
+ return sgx_epc->base + sgx_epc->size;
+}
+
#endif
Add helpers to detect if SGX EPC exists above 4g, and if so, where SGX EPC above 4g ends. Use the helpers to adjust the device memory range if SGX EPC exists above 4g. Note that SGX EPC is currently hardcoded to reside above 4g. Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com> --- hw/i386/pc.c | 10 +++++++++- include/hw/i386/sgx-epc.h | 12 ++++++++++++ 2 files changed, 21 insertions(+), 1 deletion(-)