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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id v12sm2850146pjk.13.2019.08.08.13.26.20 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Thu, 08 Aug 2019 13:26:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 8 Aug 2019 13:26:11 -0700 Message-Id: <20190808202616.13782-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190808202616.13782-1-richard.henderson@linaro.org> References: <20190808202616.13782-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH 2/7] target/arm: Use tcg_gen_deposit_i32 for PKHBT, PKHTB X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Use deposit as the composit operation to merge the bits from the two inputs. Signed-off-by: Richard Henderson --- target/arm/translate.c | 26 ++++++++++---------------- 1 file changed, 10 insertions(+), 16 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 43e005d191..94170af134 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8769,19 +8769,16 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) shift = (insn >> 7) & 0x1f; if (insn & (1 << 6)) { /* pkhtb */ - if (shift == 0) + if (shift == 0) { shift = 31; + } tcg_gen_sari_i32(tmp2, tmp2, shift); - tcg_gen_andi_i32(tmp, tmp, 0xffff0000); - tcg_gen_ext16u_i32(tmp2, tmp2); + tcg_gen_deposit_i32(tmp, tmp, tmp2, 0, 16); } else { /* pkhbt */ - if (shift) - tcg_gen_shli_i32(tmp2, tmp2, shift); - tcg_gen_ext16u_i32(tmp, tmp); - tcg_gen_andi_i32(tmp2, tmp2, 0xffff0000); + tcg_gen_shli_i32(tmp2, tmp2, shift); + tcg_gen_deposit_i32(tmp, tmp2, tmp, 0, 16); } - tcg_gen_or_i32(tmp, tmp, tmp2); tcg_temp_free_i32(tmp2); store_reg(s, rd, tmp); } else if ((insn & 0x00200020) == 0x00200000) { @@ -9817,19 +9814,16 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) shift = ((insn >> 10) & 0x1c) | ((insn >> 6) & 0x3); if (insn & (1 << 5)) { /* pkhtb */ - if (shift == 0) + if (shift == 0) { shift = 31; + } tcg_gen_sari_i32(tmp2, tmp2, shift); - tcg_gen_andi_i32(tmp, tmp, 0xffff0000); - tcg_gen_ext16u_i32(tmp2, tmp2); + tcg_gen_deposit_i32(tmp, tmp, tmp2, 0, 16); } else { /* pkhbt */ - if (shift) - tcg_gen_shli_i32(tmp2, tmp2, shift); - tcg_gen_ext16u_i32(tmp, tmp); - tcg_gen_andi_i32(tmp2, tmp2, 0xffff0000); + tcg_gen_shli_i32(tmp2, tmp2, shift); + tcg_gen_deposit_i32(tmp, tmp2, tmp, 0, 16); } - tcg_gen_or_i32(tmp, tmp, tmp2); tcg_temp_free_i32(tmp2); store_reg(s, rd, tmp); } else {