diff mbox series

[RFC,v2,36/39] target/i386: introduce SSE translators

Message ID 20190810041255.6820-37-jan.bobek@gmail.com (mailing list archive)
State New, archived
Headers show
Series rewrite MMX/SSE instruction translation | expand

Commit Message

Jan Bobek Aug. 10, 2019, 4:12 a.m. UTC 
Use the translator macros to define translators required by SSE
instructions.

Signed-off-by: Jan Bobek <jan.bobek@gmail.com>
---
 target/i386/translate.c | 33 +++++++++++++++++++++++++++++++++
 1 file changed, 33 insertions(+)
diff mbox series

Patch

diff --git a/target/i386/translate.c b/target/i386/translate.c
index 5802b324f0..12d2ac2eb5 100644
--- a/target/i386/translate.c
+++ b/target/i386/translate.c
@@ -5110,6 +5110,9 @@  static void translate_insn(
         (*gen_insn_fp)(env, s, arg1);                                   \
     }
 
+TRANSLATE_INSN_R(Mb)
+TRANSLATE_INSN_R(Md)
+
 #define TRANSLATE_INSN_RR(opR1, opR2)                                   \
     static void translate_insn_rr(opR1, opR2)(                          \
         CPUX86State *env, DisasContext *s, int modrm, int ck_cpuid_feat, \
@@ -5131,6 +5134,13 @@  static void translate_insn(
         (*gen_insn_fp)(env, s, arg1, arg2);                             \
     }
 
+TRANSLATE_INSN_RR(Pq, Nq)
+TRANSLATE_INSN_RR(Mq, Pq)
+TRANSLATE_INSN_RR(Vd, Wd)
+TRANSLATE_INSN_RR(Mq, Vq)
+TRANSLATE_INSN_RR(Mq, Vdq)
+TRANSLATE_INSN_RR(Mdq, Vdq)
+
 #define TRANSLATE_INSN_W(opW1)                                          \
     static void translate_insn_w(opW1)(                                 \
         CPUX86State *env, DisasContext *s, int modrm, int ck_cpuid_feat, \
@@ -5178,6 +5188,20 @@  TRANSLATE_INSN_WR(Qq, Pq)
 TRANSLATE_INSN_WR(Gd, Nq)
 TRANSLATE_INSN_WR(Gq, Nq)
 
+TRANSLATE_INSN_WR(Vd, Wd)
+TRANSLATE_INSN_WR(Vdq, Wdq)
+TRANSLATE_INSN_WR(Vq, UdqMq)
+TRANSLATE_INSN_WR(Wd, Vd)
+TRANSLATE_INSN_WR(Wdq, Vdq)
+TRANSLATE_INSN_WR(Gd, Udq)
+TRANSLATE_INSN_WR(Gq, Udq)
+TRANSLATE_INSN_WR(Vdq, Qq)
+TRANSLATE_INSN_WR(Vd, Ed)
+TRANSLATE_INSN_WR(Vd, Eq)
+TRANSLATE_INSN_WR(Pq, Wq)
+TRANSLATE_INSN_WR(Gd, Wd)
+TRANSLATE_INSN_WR(Gq, Wd)
+
 #define TRANSLATE_INSN_WRR(opW1, opR1, opR2)                            \
     static void translate_insn_wrr(opW1, opR1, opR2)(                   \
         CPUX86State *env, DisasContext *s, int modrm, int ck_cpuid_feat, \
@@ -5209,6 +5233,11 @@  TRANSLATE_INSN_WRR(Gd, Nq, Ib)
 TRANSLATE_INSN_WRR(Gq, Nq, Ib)
 TRANSLATE_INSN_WRR(Nq, Nq, Ib)
 
+TRANSLATE_INSN_WRR(Vd, Vd, Wd)
+TRANSLATE_INSN_WRR(Vdq, Vdq, Wdq)
+TRANSLATE_INSN_WRR(Vdq, Vq, UqMq)
+TRANSLATE_INSN_WRR(Vdq, Vdq, UdMd)
+
 #define TRANSLATE_INSN_WRRR(opW1, opR1, opR2, opR3)                     \
     static void translate_insn_wrrr(opW1, opR1, opR2, opR3)(            \
         CPUX86State *env, DisasContext *s, int modrm, int ck_cpuid_feat, \
@@ -5236,6 +5265,10 @@  TRANSLATE_INSN_WRR(Nq, Nq, Ib)
         insnop_finalize(opW1)(env, s, modrm, &ret);                     \
     }
 
+TRANSLATE_INSN_WRRR(Vd, Vd, Wd, Ib)
+TRANSLATE_INSN_WRRR(Vdq, Vdq, Wdq, Ib)
+TRANSLATE_INSN_WRRR(Pq, Pq, RdMw, Ib)
+
 #define INSN_GRP_BEGIN(grpname)                                 \
     static void translate_group(grpname)(                       \
         CPUX86State *env, DisasContext *s, int modrm)           \