| Message ID | 20190821172951.15333-32-jan.bobek@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | rewrite MMX/SSE*/AVX/AVX2 vector instruction translation | expand |
21.08.2019. 20.12, "Jan Bobek" <jan.bobek@gmail.com> је написао/ла: > > In this context, "code generators" are functions that receive decoded > instruction operands and emit TCG ops implementing the correct > instruction functionality. Introduce the naming macros first, actual > generator macros will be added later. > > Signed-off-by: Jan Bobek <jan.bobek@gmail.com> > --- I advice some caution here. Before adopting the coding approach that relies heavily on preprocessor, you should seriously evaluate not-always-so-obvious aspects of debugability and readibility of the end result. In other words, you should provide a clear and objective answer to this: What is gained and what is lost by using macros? Thanks, Aleksandar > target/i386/translate.c | 46 +++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 46 insertions(+) > > diff --git a/target/i386/translate.c b/target/i386/translate.c > index 2e78bed78f..603a5b80a1 100644 > --- a/target/i386/translate.c > +++ b/target/i386/translate.c > @@ -5331,6 +5331,52 @@ INSNOP_LDST(xmm, Mhq) > tcg_temp_free_i64(r64); > } > > +/* > + * Code generators > + */ > +#define gen_insn(mnem, argc, ...) \ > + glue(gen_insn, argc)(mnem, ## __VA_ARGS__) > +#define gen_insn0(mnem) \ > + gen_ ## mnem ## _0 > +#define gen_insn1(mnem, opT1) \ > + gen_ ## mnem ## _1 ## opT1 > +#define gen_insn2(mnem, opT1, opT2) \ > + gen_ ## mnem ## _2 ## opT1 ## opT2 > +#define gen_insn3(mnem, opT1, opT2, opT3) \ > + gen_ ## mnem ## _3 ## opT1 ## opT2 ## opT3 > +#define gen_insn4(mnem, opT1, opT2, opT3, opT4) \ > + gen_ ## mnem ## _4 ## opT1 ## opT2 ## opT3 ## opT4 > +#define gen_insn5(mnem, opT1, opT2, opT3, opT4, opT5) \ > + gen_ ## mnem ## _5 ## opT1 ## opT2 ## opT3 ## opT4 ## opT5 > + > +#define GEN_INSN0(mnem) \ > + static void gen_insn0(mnem)( \ > + CPUX86State *env, DisasContext *s) > +#define GEN_INSN1(mnem, opT1) \ > + static void gen_insn1(mnem, opT1)( \ > + CPUX86State *env, DisasContext *s, \ > + insnop_arg_t(opT1) arg1) > +#define GEN_INSN2(mnem, opT1, opT2) \ > + static void gen_insn2(mnem, opT1, opT2)( \ > + CPUX86State *env, DisasContext *s, \ > + insnop_arg_t(opT1) arg1, insnop_arg_t(opT2) arg2) > +#define GEN_INSN3(mnem, opT1, opT2, opT3) \ > + static void gen_insn3(mnem, opT1, opT2, opT3)( \ > + CPUX86State *env, DisasContext *s, \ > + insnop_arg_t(opT1) arg1, insnop_arg_t(opT2) arg2, \ > + insnop_arg_t(opT3) arg3) > +#define GEN_INSN4(mnem, opT1, opT2, opT3, opT4) \ > + static void gen_insn4(mnem, opT1, opT2, opT3, opT4)( \ > + CPUX86State *env, DisasContext *s, \ > + insnop_arg_t(opT1) arg1, insnop_arg_t(opT2) arg2, \ > + insnop_arg_t(opT3) arg3, insnop_arg_t(opT4) arg4) > +#define GEN_INSN5(mnem, opT1, opT2, opT3, opT4, opT5) \ > + static void gen_insn5(mnem, opT1, opT2, opT3, opT4, opT5)( \ > + CPUX86State *env, DisasContext *s, \ > + insnop_arg_t(opT1) arg1, insnop_arg_t(opT2) arg2, \ > + insnop_arg_t(opT3) arg3, insnop_arg_t(opT4) arg4, \ > + insnop_arg_t(opT5) arg5) > + > static void gen_sse_ng(CPUX86State *env, DisasContext *s, int b) > { > enum { > -- > 2.20.1 > >
diff --git a/target/i386/translate.c b/target/i386/translate.c index 2e78bed78f..603a5b80a1 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -5331,6 +5331,52 @@ INSNOP_LDST(xmm, Mhq) tcg_temp_free_i64(r64); } +/* + * Code generators + */ +#define gen_insn(mnem, argc, ...) \ + glue(gen_insn, argc)(mnem, ## __VA_ARGS__) +#define gen_insn0(mnem) \ + gen_ ## mnem ## _0 +#define gen_insn1(mnem, opT1) \ + gen_ ## mnem ## _1 ## opT1 +#define gen_insn2(mnem, opT1, opT2) \ + gen_ ## mnem ## _2 ## opT1 ## opT2 +#define gen_insn3(mnem, opT1, opT2, opT3) \ + gen_ ## mnem ## _3 ## opT1 ## opT2 ## opT3 +#define gen_insn4(mnem, opT1, opT2, opT3, opT4) \ + gen_ ## mnem ## _4 ## opT1 ## opT2 ## opT3 ## opT4 +#define gen_insn5(mnem, opT1, opT2, opT3, opT4, opT5) \ + gen_ ## mnem ## _5 ## opT1 ## opT2 ## opT3 ## opT4 ## opT5 + +#define GEN_INSN0(mnem) \ + static void gen_insn0(mnem)( \ + CPUX86State *env, DisasContext *s) +#define GEN_INSN1(mnem, opT1) \ + static void gen_insn1(mnem, opT1)( \ + CPUX86State *env, DisasContext *s, \ + insnop_arg_t(opT1) arg1) +#define GEN_INSN2(mnem, opT1, opT2) \ + static void gen_insn2(mnem, opT1, opT2)( \ + CPUX86State *env, DisasContext *s, \ + insnop_arg_t(opT1) arg1, insnop_arg_t(opT2) arg2) +#define GEN_INSN3(mnem, opT1, opT2, opT3) \ + static void gen_insn3(mnem, opT1, opT2, opT3)( \ + CPUX86State *env, DisasContext *s, \ + insnop_arg_t(opT1) arg1, insnop_arg_t(opT2) arg2, \ + insnop_arg_t(opT3) arg3) +#define GEN_INSN4(mnem, opT1, opT2, opT3, opT4) \ + static void gen_insn4(mnem, opT1, opT2, opT3, opT4)( \ + CPUX86State *env, DisasContext *s, \ + insnop_arg_t(opT1) arg1, insnop_arg_t(opT2) arg2, \ + insnop_arg_t(opT3) arg3, insnop_arg_t(opT4) arg4) +#define GEN_INSN5(mnem, opT1, opT2, opT3, opT4, opT5) \ + static void gen_insn5(mnem, opT1, opT2, opT3, opT4, opT5)( \ + CPUX86State *env, DisasContext *s, \ + insnop_arg_t(opT1) arg1, insnop_arg_t(opT2) arg2, \ + insnop_arg_t(opT3) arg3, insnop_arg_t(opT4) arg4, \ + insnop_arg_t(opT5) arg5) + static void gen_sse_ng(CPUX86State *env, DisasContext *s, int b) { enum {
In this context, "code generators" are functions that receive decoded instruction operands and emit TCG ops implementing the correct instruction functionality. Introduce the naming macros first, actual generator macros will be added later. Signed-off-by: Jan Bobek <jan.bobek@gmail.com> --- target/i386/translate.c | 46 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+)