Message ID | 20190821172951.15333-34-jan.bobek@gmail.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show
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X-Received-From: 2607:f8b0:4864:20::c43 Subject: [Qemu-devel] [RFC PATCH v4 33/75] target/i386: introduce gvec-based code generator macros X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: <qemu-devel.nongnu.org> List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe> List-Archive: <https://lists.nongnu.org/archive/html/qemu-devel> List-Post: <mailto:qemu-devel@nongnu.org> List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help> List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=subscribe> Cc: Jan Bobek <jan.bobek@gmail.com>, =?utf-8?q?Alex_Benn=C3=A9e?= <alex.bennee@linaro.org>, Richard Henderson <richard.henderson@linaro.org> Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org> |
Series |
rewrite MMX/SSE*/AVX/AVX2 vector instruction translation
|
expand
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diff --git a/target/i386/translate.c b/target/i386/translate.c index 046914578b..eab36963c3 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -24,6 +24,7 @@ #include "exec/exec-all.h" #include "tcg-gvec-desc.h" #include "tcg-op.h" +#include "tcg-op-gvec.h" #include "exec/cpu_ldst.h" #include "exec/translator.h" @@ -5537,6 +5538,30 @@ INSNOP_LDST(xmm, Mhq) tcg_temp_free_i32(arg4_r32); \ } +#define MM_OPRSZ sizeof(MMXReg) +#define MM_MAXSZ sizeof(MMXReg) +#define XMM_OPRSZ (!(s->prefix & PREFIX_VEX) ? sizeof(XMMReg) : \ + s->vex_l ? sizeof(XMMReg) : \ + sizeof(XMMReg)) +#define XMM_MAXSZ (!(s->prefix & PREFIX_VEX) ? sizeof(XMMReg) : \ + sizeof(YMMReg)) + +#define DEF_GEN_INSN2_GVEC(mnem, opT1, opT2, gvec, ...) \ + GEN_INSN2(mnem, opT1, opT2) \ + { \ + gen_gvec_ ## gvec(arg1, arg2, ## __VA_ARGS__); \ + } +#define DEF_GEN_INSN3_GVEC(mnem, opT1, opT2, opT3, gvec, ...) \ + GEN_INSN3(mnem, opT1, opT2, opT3) \ + { \ + gen_gvec_ ## gvec(arg1, arg2, arg3, ## __VA_ARGS__); \ + } +#define DEF_GEN_INSN4_GVEC(mnem, opT1, opT2, opT3, opT4, gvec, ...) \ + GEN_INSN4(mnem, opT1, opT2, opT3, opT4) \ + { \ + gen_gvec_ ## gvec(arg1, arg2, arg3, arg4, ## __VA_ARGS__); \ + } + static void gen_sse_ng(CPUX86State *env, DisasContext *s, int b) { enum {
Code generators defined using these macros rely on a gvec operation (i.e. tcg_gen_gvec_*). Signed-off-by: Jan Bobek <jan.bobek@gmail.com> --- target/i386/translate.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+)