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X-Received-From: 2607:f8b0:4864:20::b43 Subject: [Qemu-devel] [RFC PATCH v4 47/75] target/i386: introduce SSE3 vector instructions to sse-opcode.inc.h X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jan Bobek , =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Add all the SSE3 vector instruction entries to sse-opcode.inc.h. Signed-off-by: Jan Bobek --- target/i386/sse-opcode.inc.h | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/target/i386/sse-opcode.inc.h b/target/i386/sse-opcode.inc.h index 6df5fda010..84785a4e04 100644 --- a/target/i386/sse-opcode.inc.h +++ b/target/i386/sse-opcode.inc.h @@ -341,6 +341,19 @@ * NP 0F AE /7 CLFLUSH m8 * NP 0F AE /5 LFENCE * NP 0F AE /6 MFENCE + * + * SSE3 Instructions + * ------------------ + * F2 0F F0 /r LDDQU xmm1, m128 + * F3 0F 16 /r MOVSHDUP xmm1, xmm2/m128 + * F3 0F 12 /r MOVSLDUP xmm1, xmm2/m128 + * F2 0F 12 /r MOVDDUP xmm1, xmm2/m64 + * F2 0F 7C /r HADDPS xmm1, xmm2/m128 + * 66 0F 7C /r HADDPD xmm1, xmm2/m128 + * F2 0F 7D /r HSUBPS xmm1, xmm2/m128 + * 66 0F 7D /r HSUBPD xmm1, xmm2/m128 + * F2 0F D0 /r ADDSUBPS xmm1, xmm2/m128 + * 66 0F D0 /r ADDSUBPD xmm1, xmm2/m128 */ OPCODE(movd, LEG(NP, 0F, 0, 0x6e), MMX, WR, Pq, Ed) @@ -389,6 +402,10 @@ OPCODE(movmskps, LEG(NP, 0F, 0, 0x50), SSE, WR, Gd, Udq) OPCODE(movmskps, LEG(NP, 0F, 1, 0x50), SSE, WR, Gq, Udq) OPCODE(movmskpd, LEG(66, 0F, 0, 0x50), SSE2, WR, Gd, Udq) OPCODE(movmskpd, LEG(66, 0F, 1, 0x50), SSE2, WR, Gq, Udq) +OPCODE(lddqu, LEG(F2, 0F, 0, 0xf0), SSE3, WR, Vdq, Mdq) +OPCODE(movshdup, LEG(F3, 0F, 0, 0x16), SSE3, WR, Vdq, Wdq) +OPCODE(movsldup, LEG(F3, 0F, 0, 0x12), SSE3, WR, Vdq, Wdq) +OPCODE(movddup, LEG(F2, 0F, 0, 0x12), SSE3, WR, Vdq, Wq) OPCODE(paddb, LEG(NP, 0F, 0, 0xfc), MMX, WRR, Pq, Pq, Qq) OPCODE(paddb, LEG(66, 0F, 0, 0xfc), SSE2, WRR, Vdq, Vdq, Wdq) OPCODE(paddw, LEG(NP, 0F, 0, 0xfd), MMX, WRR, Pq, Pq, Qq) @@ -409,6 +426,8 @@ OPCODE(addps, LEG(NP, 0F, 0, 0x58), SSE, WRR, Vdq, Vdq, Wdq) OPCODE(addpd, LEG(66, 0F, 0, 0x58), SSE2, WRR, Vdq, Vdq, Wdq) OPCODE(addss, LEG(F3, 0F, 0, 0x58), SSE, WRR, Vd, Vd, Wd) OPCODE(addsd, LEG(F2, 0F, 0, 0x58), SSE2, WRR, Vq, Vq, Wq) +OPCODE(haddps, LEG(F2, 0F, 0, 0x7c), SSE3, WRR, Vdq, Vdq, Wdq) +OPCODE(haddpd, LEG(66, 0F, 0, 0x7c), SSE3, WRR, Vdq, Vdq, Wdq) OPCODE(psubb, LEG(NP, 0F, 0, 0xf8), MMX, WRR, Pq, Pq, Qq) OPCODE(psubb, LEG(66, 0F, 0, 0xf8), SSE2, WRR, Vdq, Vdq, Wdq) OPCODE(psubw, LEG(NP, 0F, 0, 0xf9), MMX, WRR, Pq, Pq, Qq) @@ -429,6 +448,10 @@ OPCODE(subps, LEG(NP, 0F, 0, 0x5c), SSE, WRR, Vdq, Vdq, Wdq) OPCODE(subpd, LEG(66, 0F, 0, 0x5c), SSE2, WRR, Vdq, Vdq, Wdq) OPCODE(subss, LEG(F3, 0F, 0, 0x5c), SSE, WRR, Vd, Vd, Wd) OPCODE(subsd, LEG(F2, 0F, 0, 0x5c), SSE2, WRR, Vq, Vq, Wq) +OPCODE(hsubps, LEG(F2, 0F, 0, 0x7d), SSE3, WRR, Vdq, Vdq, Wdq) +OPCODE(hsubpd, LEG(66, 0F, 0, 0x7d), SSE3, WRR, Vdq, Vdq, Wdq) +OPCODE(addsubps, LEG(F2, 0F, 0, 0xd0), SSE3, WRR, Vdq, Vdq, Wdq) +OPCODE(addsubpd, LEG(66, 0F, 0, 0xd0), SSE3, WRR, Vdq, Vdq, Wdq) OPCODE(pmullw, LEG(NP, 0F, 0, 0xd5), MMX, WRR, Pq, Pq, Qq) OPCODE(pmullw, LEG(66, 0F, 0, 0xd5), SSE2, WRR, Vdq, Vdq, Wdq) OPCODE(pmulhw, LEG(NP, 0F, 0, 0xe5), MMX, WRR, Pq, Pq, Qq)