From patchwork Sun Sep 1 14:21:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Tao Xu X-Patchwork-Id: 11125299 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 819D5112C for ; Sun, 1 Sep 2019 14:30:31 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 62BFB22CE9 for ; Sun, 1 Sep 2019 14:30:31 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 62BFB22CE9 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:57810 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i4Qs9-0005Dm-Js for patchwork-qemu-devel@patchwork.kernel.org; Sun, 01 Sep 2019 10:30:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39553) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i4Qje-0004h0-MI for qemu-devel@nongnu.org; Sun, 01 Sep 2019 10:21:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i4Qjd-0004oh-CA for qemu-devel@nongnu.org; Sun, 01 Sep 2019 10:21:42 -0400 Received: from mga12.intel.com ([192.55.52.136]:16719) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1i4Qjd-0004jJ-1Y for qemu-devel@nongnu.org; Sun, 01 Sep 2019 10:21:41 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 01 Sep 2019 07:21:40 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,455,1559545200"; d="scan'208";a="211453123" Received: from tao-optiplex-7060.sh.intel.com ([10.239.159.36]) by fmsmga002.fm.intel.com with ESMTP; 01 Sep 2019 07:21:38 -0700 From: Tao Xu To: imammedo@redhat.com, eblake@redhat.com, ehabkost@redhat.com Date: Sun, 1 Sep 2019 22:21:16 +0800 Message-Id: <20190901142119.20482-9-tao3.xu@intel.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190901142119.20482-1-tao3.xu@intel.com> References: <20190901142119.20482-1-tao3.xu@intel.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 192.55.52.136 Subject: [Qemu-devel] [PATCH v10 08/11] hmat acpi: Build Memory Side Cache Information Structure(s) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jingqi.liu@intel.com, tao3.xu@intel.com, fan.du@intel.com, qemu-devel@nongnu.org, daniel@linux.ibm.com, Jonathan Cameron , dan.j.williams@intel.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Liu Jingqi This structure describes memory side cache information for memory proximity domains if the memory side cache is present and the physical device forms the memory side cache. The software could use this information to effectively place the data in memory to maximize the performance of the system memory that use the memory side cache. Reviewed-by: Daniel Black Reviewed-by: Jonathan Cameron Signed-off-by: Liu Jingqi Signed-off-by: Tao Xu --- No changes in v10 --- hw/acpi/hmat.c | 64 ++++++++++++++++++++++++++++++++++++++++- hw/acpi/hmat.h | 17 +++++++++++ include/qemu/typedefs.h | 1 + include/sysemu/numa.h | 5 ++++ 4 files changed, 86 insertions(+), 1 deletion(-) diff --git a/hw/acpi/hmat.c b/hw/acpi/hmat.c index 27e7ff63f8..71d8950241 100644 --- a/hw/acpi/hmat.c +++ b/hw/acpi/hmat.c @@ -134,14 +134,63 @@ static void build_hmat_lb(GArray *table_data, HMAT_LB_Info *hmat_lb, } } +/* ACPI 6.3: 5.2.27.5 Memory Side Cache Information Structure: Table 5-147 */ +static void build_hmat_cache(GArray *table_data, HMAT_Cache_Info *hmat_cache) +{ + /* + * Cache Attributes: Bits [3:0] – Total Cache Levels + * for this Memory Proximity Domain + */ + uint32_t cache_attr = hmat_cache->total_levels & 0xF; + + /* Bits [7:4] : Cache Level described in this structure */ + cache_attr |= (hmat_cache->level & 0xF) << 4; + + /* Bits [11:8] - Cache Associativity */ + cache_attr |= (hmat_cache->associativity & 0xF) << 8; + + /* Bits [15:12] - Write Policy */ + cache_attr |= (hmat_cache->write_policy & 0xF) << 12; + + /* Bits [31:16] - Cache Line size in bytes */ + cache_attr |= (hmat_cache->line_size & 0xFFFF) << 16; + + cache_attr = cpu_to_le32(cache_attr); + + /* Type */ + build_append_int_noprefix(table_data, 2, 2); + /* Reserved */ + build_append_int_noprefix(table_data, 0, 2); + /* Length */ + build_append_int_noprefix(table_data, 32, 4); + /* Proximity Domain for the Memory */ + build_append_int_noprefix(table_data, hmat_cache->mem_proximity, 4); + /* Reserved */ + build_append_int_noprefix(table_data, 0, 4); + /* Memory Side Cache Size */ + build_append_int_noprefix(table_data, hmat_cache->size, 8); + /* Cache Attributes */ + build_append_int_noprefix(table_data, cache_attr, 4); + /* Reserved */ + build_append_int_noprefix(table_data, 0, 2); + /* + * Number of SMBIOS handles (n) + * Linux kernel uses Memory Side Cache Information Structure + * without SMBIOS entries for now, so set Number of SMBIOS handles + * as 0. + */ + build_append_int_noprefix(table_data, 0, 2); +} + /* Build HMAT sub table structures */ static void hmat_build_table_structs(GArray *table_data, NumaState *nstat) { uint16_t flags; uint32_t num_initiator = 0; uint32_t initiator_pxm[MAX_NODES]; - int i, hrchy, type; + int i, hrchy, type, level; HMAT_LB_Info *numa_hmat_lb; + HMAT_Cache_Info *numa_hmat_cache; for (i = 0; i < nstat->num_nodes; i++) { flags = 0; @@ -175,6 +224,19 @@ static void hmat_build_table_structs(GArray *table_data, NumaState *nstat) } } } + + /* + * ACPI 6.3: 5.2.27.5 Memory Side Cache Information Structure: + * Table 5-147 + */ + for (i = 0; i < nstat->num_nodes; i++) { + for (level = 0; level <= MAX_HMAT_CACHE_LEVEL; level++) { + numa_hmat_cache = nstat->hmat_cache[i][level]; + if (numa_hmat_cache) { + build_hmat_cache(table_data, numa_hmat_cache); + } + } + } } void build_hmat(GArray *table_data, BIOSLinker *linker, NumaState *nstat) diff --git a/hw/acpi/hmat.h b/hw/acpi/hmat.h index 79ddb873c1..1373f22b27 100644 --- a/hw/acpi/hmat.h +++ b/hw/acpi/hmat.h @@ -81,6 +81,23 @@ struct HMAT_LB_Info { uint16_t bandwidth[MAX_NODES][MAX_NODES]; }; +struct HMAT_Cache_Info { + /* The memory proximity domain to which the memory belongs. */ + uint32_t mem_proximity; + /* Size of memory side cache in bytes. */ + uint64_t size; + /* Total cache levels for this memory proximity domain. */ + uint8_t total_levels; + /* Cache level described in this structure. */ + uint8_t level; + /* Cache Associativity: None/Direct Mapped/Comple Cache Indexing */ + uint8_t associativity; + /* Write Policy: None/Write Back(WB)/Write Through(WT) */ + uint8_t write_policy; + /* Cache Line size in bytes. */ + uint16_t line_size; +}; + void build_hmat(GArray *table_data, BIOSLinker *linker, NumaState *nstat); #endif diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h index ad8955ecd8..426fd503f0 100644 --- a/include/qemu/typedefs.h +++ b/include/qemu/typedefs.h @@ -49,6 +49,7 @@ typedef struct FWCfgEntry FWCfgEntry; typedef struct FWCfgIoState FWCfgIoState; typedef struct FWCfgMemState FWCfgMemState; typedef struct FWCfgState FWCfgState; +typedef struct HMAT_Cache_Info HMAT_Cache_Info; typedef struct HMAT_LB_Info HMAT_LB_Info; typedef struct HostMemoryBackend HostMemoryBackend; typedef struct HVFX86EmulatorState HVFX86EmulatorState; diff --git a/include/sysemu/numa.h b/include/sysemu/numa.h index 8dbf76c5b4..dc48d39439 100644 --- a/include/sysemu/numa.h +++ b/include/sysemu/numa.h @@ -35,6 +35,8 @@ enum { #define HMAT_LB_LEVELS (HMAT_LB_MEM_CACHE_3RD_LEVEL + 1) #define HMAT_LB_TYPES (HMAT_LB_DATA_WRITE_BANDWIDTH + 1) +#define MAX_HMAT_CACHE_LEVEL 3 + struct NodeInfo { uint64_t node_mem; struct HostMemoryBackend *node_memdev; @@ -65,6 +67,9 @@ struct NumaState { /* NUMA modes HMAT Locality Latency and Bandwidth Information */ HMAT_LB_Info *hmat_lb[HMAT_LB_LEVELS][HMAT_LB_TYPES]; + + /* Memory Side Cache Information Structure */ + HMAT_Cache_Info *hmat_cache[MAX_NODES][MAX_HMAT_CACHE_LEVEL + 1]; }; typedef struct NumaState NumaState;