From patchwork Wed Sep 4 17:13:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11131153 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7214A15E9 for ; Wed, 4 Sep 2019 17:28:11 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4835E2087E for ; Wed, 4 Sep 2019 17:28:11 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="nXyUKui9" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4835E2087E Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=amsat.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35920 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5Z4j-0007os-O0 for patchwork-qemu-devel@patchwork.kernel.org; Wed, 04 Sep 2019 13:28:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48537) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5Yqg-0001dr-9I for qemu-devel@nongnu.org; Wed, 04 Sep 2019 13:13:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i5Yqe-00077a-Fj for qemu-devel@nongnu.org; Wed, 04 Sep 2019 13:13:38 -0400 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]:37481) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i5Yqe-000771-8P; Wed, 04 Sep 2019 13:13:36 -0400 Received: by mail-wr1-x444.google.com with SMTP id z11so22107793wrt.4; Wed, 04 Sep 2019 10:13:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rnPX/CkCbP5cUR+Jpf6ypoo9OA8ST+okjOPSeePlPKk=; b=nXyUKui9x9H0GwOqTGL8jqK3/3LURKyF4b8QwEoQ3mLJlf8zfaY6DrGlj8LXlCuRNH 4WYb1TX1NdW8pmcdvovw0iqDM7rwYcBQ+GlF3FDmpp/6WtzlINcIeozhrwL12QoeHnPn +Oxc+UubrO3NCVe8Q+lW1XMBwExJQUs5mpb+2i/PK4sibcQdzR6mUfb4HicRFhIA4QJY CQoVU1Jf4CwdZqiV8bi6hjCYGmhhrfopLkVK1mQSYIqoMIQqgNn1pGCbEC1dhHEJtuEP cEUVkwj7UwWUWozKCQo9Hr8r/hsRRwG9cuppjladKzq4upUaio3bzLRbki2ffwTxEg0Q RGVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=rnPX/CkCbP5cUR+Jpf6ypoo9OA8ST+okjOPSeePlPKk=; b=E57i7jaExaQ7BuB3/XXCUHft8IO5kGRK0Ahw++v5wRdu3B3nj2y1p6arH7snemgzNE YkV6GGqT7OpADo4v+8gpO0wfcaxaiMJGub/xTJcIuyZIPdDGZL5INYHwEB5LDJynUSq1 8DOgjnDyb3YKHmLlT/SO/bUPzgeIvGNfrRtgdswXrrtEH0XdKarsy63l+VOelg17IAxx m1sAKgnAsJ+I1hkLXHXuu/yxUBVKjF2uJhsJG5eev15cwEp0tqyIEuK+UHtnVrv3053I HZx6NAvQVcJavv3FcEPH8dmcSY+wSD/cUFP5vYhiq7q2mGmPbVVDcmASh2rhQvYZXyzL pbIA== X-Gm-Message-State: APjAAAWvbZxV2X8wApOIpMU+fItwUTNN94vdMKOfk6RsyIdXUe6W1III Q25dE2YbYPqMNe12VSpCaoA= X-Google-Smtp-Source: APXvYqwEi9l8a4GqD7gjT74ZnVq526YzVZkty7zA4ZxrLeR16ajKB9ENuB6xeSweJ4v4fz1ppxVgDg== X-Received: by 2002:a5d:460e:: with SMTP id t14mr51954710wrq.171.1567617215265; Wed, 04 Sep 2019 10:13:35 -0700 (PDT) Received: from x1w.redhat.com ([195.166.127.210]) by smtp.gmail.com with ESMTPSA id p19sm2339512wmg.31.2019.09.04.10.13.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 10:13:34 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Peter Maydell , Esteban Bosse , Andrew Baumann , qemu-devel@nongnu.org, Pekka Enberg , =?utf-8?q?Zolt=C3=A1n_Baldaszti?= Date: Wed, 4 Sep 2019 19:13:11 +0200 Message-Id: <20190904171315.8354-11-f4bug@amsat.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190904171315.8354-1-f4bug@amsat.org> References: <20190904171315.8354-1-f4bug@amsat.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 Subject: [Qemu-devel] [PATCH 10/14] hw/arm/raspi: Define various blocks base addresses X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, Clement Deschamps , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Luc Michel Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" The Raspberry firmware is closed-source. While running it, it accesses various I/O registers. Logging these accesses as UNIMP (unimplemented) help to understand what the firmware is doing (ideally we want it able to boot a Linux kernel). Document various blocks we might use later. Adresses and names based on: https://github.com/hermanhermitage/videocoreiv/wiki/MMIO-Register-map Signed-off-by: Philippe Mathieu-Daudé --- include/hw/arm/raspi_platform.h | 49 +++++++++++++++++++++++++++------ 1 file changed, 40 insertions(+), 9 deletions(-) diff --git a/include/hw/arm/raspi_platform.h b/include/hw/arm/raspi_platform.h index 069edab526..c6f4985522 100644 --- a/include/hw/arm/raspi_platform.h +++ b/include/hw/arm/raspi_platform.h @@ -25,42 +25,73 @@ #ifndef HW_ARM_RASPI_PLATFORM_H #define HW_ARM_RASPI_PLATFORM_H -#define MCORE_OFFSET 0x0000 /* Fake frame buffer device - * (the multicore sync block) */ -#define IC0_OFFSET 0x2000 +#define MSYNC_OFFSET 0x0000 /* Multicore Sync Block */ +#define CCPT_OFFSET 0x1000 /* Compact Camera Port 2 TX */ +#define INTE_OFFSET 0x2000 /* VC Interrupt controller */ #define ST_OFFSET 0x3000 /* System Timer */ +#define TXP_OFFSET 0x4000 +#define JPEG_OFFSET 0x5000 #define MPHI_OFFSET 0x6000 /* Message-based Parallel Host Intf. */ #define DMA_OFFSET 0x7000 /* DMA controller, channels 0-14 */ -#define ARM_OFFSET 0xB000 /* BCM2708 ARM control block */ +#define ARBA_OFFSET 0x9000 +#define BRDG_OFFSET 0xa000 +#define ARM_OFFSET 0xB000 /* ARM control block */ #define ARMCTRL_OFFSET (ARM_OFFSET + 0x000) #define ARMCTRL_IC_OFFSET (ARM_OFFSET + 0x200) /* Interrupt controller */ -#define ARMCTRL_TIMER0_1_OFFSET (ARM_OFFSET + 0x400) /* Timer 0 and 1 */ +#define ARMCTRL_TIMER0_1_OFFSET (ARM_OFFSET + 0x400) /* Timer 0 and 1 (SP804) */ #define ARMCTRL_0_SBM_OFFSET (ARM_OFFSET + 0x800) /* User 0 (ARM) Semaphores * Doorbells & Mailboxes */ #define PM_OFFSET 0x100000 /* Power Management, Reset controller * and Watchdog registers */ #define CPRMAN_OFFSET 0x101000 /* Clock Management */ +#define A2W_OFFSET 0x102000 #define AVS_OFFSET 0x103000 /* Audio Video Standard */ #define RNG_OFFSET 0x104000 #define GPIO_OFFSET 0x200000 -#define UART0_OFFSET 0x201000 -#define MMCI0_OFFSET 0x202000 -#define I2S_OFFSET 0x203000 -#define SPI0_OFFSET 0x204000 +#define UART0_OFFSET 0x201000 /* PL011 */ +#define MMCI0_OFFSET 0x202000 /* Legacy MMC */ +#define I2S_OFFSET 0x203000 /* PCM */ +#define SPI0_OFFSET 0x204000 /* SPI master */ #define BSC0_OFFSET 0x205000 /* BSC0 I2C/TWI */ +#define PIXV0_OFFSET 0x206000 +#define PIXV1_OFFSET 0x207000 +#define DPI_OFFSET 0x208000 +#define DSI0_OFFSET 0x209000 /* Display Serial Interface */ +#define PWM_OFFSET 0x20c000 +#define PERM_OFFSET 0x20d000 +#define TEC_OFFSET 0x20e000 #define OTP_OFFSET 0x20f000 +#define SLIM_OFFSET 0x100000 /* SLIMbus */ +#define CPG_OFFSET 0x110000 #define AVSP_OFFSET 0x130000 #define BSC_SL_OFFSET 0x214000 /* SPI slave */ +#define THERMAL_OFFSET 0x212000 #define AUX_OFFSET 0x215000 /* AUX: UART1/SPI1/SPI2 */ #define EMMC1_OFFSET 0x300000 +#define EMMC2_OFFSET 0x340000 +#define HVS_OFFSET 0x400000 #define SMI_OFFSET 0x600000 +#define DSI1_OFFSET 0x700000 +#define UCAM_OFFSET 0x800000 +#define CMI_OFFSET 0x802000 #define BSC1_OFFSET 0x804000 /* BSC1 I2C/TWI */ #define BSC2_OFFSET 0x805000 /* BSC2 I2C/TWI */ +#define VECA_OFFSET 0x806000 +#define PIXV2_OFFSET 0x807000 +#define HDMI_OFFSET 0x808000 +#define HDCP_OFFSET 0x809000 +#define ARBR0_OFFSET 0x80a000 #define DBUS_OFFSET 0x900000 #define AVE0_OFFSET 0x910000 #define USB_OTG_OFFSET 0x980000 /* DTC_OTG USB controller */ +#define V3D_OFFSET 0xc00000 #define SDRAMC_OFFSET 0xe00000 +#define L2CC_OFFSET 0xe01000 /* Level 2 Cache controller */ +#define L1CC_OFFSET 0xe02000 /* Level 1 Cache controller */ +#define ARBR1_OFFSET 0xe04000 #define DMA15_OFFSET 0xE05000 /* DMA controller, channel 15 */ +#define DCRC_OFFSET 0xe07000 +#define AXIP_OFFSET 0xe08000 /* GPU interrupts */ #define INTERRUPT_TIMER0 0