@@ -10240,6 +10240,18 @@ static bool trans_SB(DisasContext *s, arg_SB *a)
return true;
}
+static bool trans_SETEND(DisasContext *s, arg_SETEND *a)
+{
+ if (!ENABLE_ARCH_6) {
+ return false;
+ }
+ if (a->E != (s->be_data == MO_BE)) {
+ gen_helper_setend(cpu_env);
+ s->base.is_jmp = DISAS_UPDATE;
+ }
+ return true;
+}
+
/*
* Legacy decoder.
*/
@@ -10325,15 +10337,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
return; /* v7MP: Unallocated memory hint: must NOP */
}
- if ((insn & 0x0ffffdff) == 0x01010000) {
- ARCH(6);
- /* setend */
- if (((insn >> 9) & 1) != !!(s->be_data == MO_BE)) {
- gen_helper_setend(cpu_env);
- s->base.is_jmp = DISAS_UPDATE;
- }
- return;
- } else if ((insn & 0x0e000f00) == 0x0c000100) {
+ if ((insn & 0x0e000f00) == 0x0c000100) {
if (arm_dc_feature(s, ARM_FEATURE_IWMMXT)) {
/* iWMMXt register transfer. */
if (extract32(s->c15_cpar, 1, 1)) {
@@ -24,6 +24,7 @@
&empty !extern
&i !extern imm
+&setend E
# Branch with Link and Exchange
@@ -50,3 +51,6 @@ DSB 1111 0101 0111 1111 1111 0000 0100 ----
DMB 1111 0101 0111 1111 1111 0000 0101 ----
ISB 1111 0101 0111 1111 1111 0000 0110 ----
SB 1111 0101 0111 1111 1111 0000 0111 0000
+
+# Set Endianness
+SETEND 1111 0001 0000 0001 0000 00 E:1 0 0000 0000 &setend