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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.31.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:31:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:30:27 -0700 Message-Id: <20190904193059.26202-38-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH v4 37/69] target/arm: Convert SETEND X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/arm/translate.c | 22 +++++++++++++--------- target/arm/a32-uncond.decode | 4 ++++ 2 files changed, 17 insertions(+), 9 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 664ea281f8..a599da96e1 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10240,6 +10240,18 @@ static bool trans_SB(DisasContext *s, arg_SB *a) return true; } +static bool trans_SETEND(DisasContext *s, arg_SETEND *a) +{ + if (!ENABLE_ARCH_6) { + return false; + } + if (a->E != (s->be_data == MO_BE)) { + gen_helper_setend(cpu_env); + s->base.is_jmp = DISAS_UPDATE; + } + return true; +} + /* * Legacy decoder. */ @@ -10325,15 +10337,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) return; /* v7MP: Unallocated memory hint: must NOP */ } - if ((insn & 0x0ffffdff) == 0x01010000) { - ARCH(6); - /* setend */ - if (((insn >> 9) & 1) != !!(s->be_data == MO_BE)) { - gen_helper_setend(cpu_env); - s->base.is_jmp = DISAS_UPDATE; - } - return; - } else if ((insn & 0x0e000f00) == 0x0c000100) { + if ((insn & 0x0e000f00) == 0x0c000100) { if (arm_dc_feature(s, ARM_FEATURE_IWMMXT)) { /* iWMMXt register transfer. */ if (extract32(s->c15_cpar, 1, 1)) { diff --git a/target/arm/a32-uncond.decode b/target/arm/a32-uncond.decode index de611e8aff..32253b4f9a 100644 --- a/target/arm/a32-uncond.decode +++ b/target/arm/a32-uncond.decode @@ -24,6 +24,7 @@ &empty !extern &i !extern imm +&setend E # Branch with Link and Exchange @@ -50,3 +51,6 @@ DSB 1111 0101 0111 1111 1111 0000 0100 ---- DMB 1111 0101 0111 1111 1111 0000 0101 ---- ISB 1111 0101 0111 1111 1111 0000 0110 ---- SB 1111 0101 0111 1111 1111 0000 0111 0000 + +# Set Endianness +SETEND 1111 0001 0000 0001 0000 00 E:1 0 0000 0000 &setend