Message ID | 20190904193059.26202-67-richard.henderson@linaro.org (mailing list archive) |
---|---|
State | New, archived |
Headers | show
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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.32.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:32:24 -0700 (PDT) From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:30:56 -0700 Message-Id: <20190904193059.26202-67-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::435 Subject: [Qemu-devel] [PATCH v4 66/69] target/arm: Convert T16, Unconditional branch X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: <qemu-devel.nongnu.org> List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe> List-Archive: <https://lists.nongnu.org/archive/html/qemu-devel> List-Post: <mailto:qemu-devel@nongnu.org> List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help> List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=subscribe> Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org> |
Series |
target/arm: Convert aa32 base isa to decodetree
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expand
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diff --git a/target/arm/translate.c b/target/arm/translate.c index 4f4c77fc89..3238ccbf1e 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10736,7 +10736,6 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) static void disas_thumb_insn(DisasContext *s, uint32_t insn) { - uint32_t val; int32_t offset; TCGv_i32 tmp; TCGv_i32 tmp2; @@ -10780,12 +10779,8 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) gen_bx(s, tmp); break; } - /* unconditional branch */ - val = read_pc(s); - offset = ((int32_t)insn << 21) >> 21; - val += offset << 1; - gen_jmp(s, val); - break; + /* unconditional branch, in decodetree */ + goto illegal_op; case 15: /* thumb_insn_is_16bit() ensures we can't get here for diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 0b4da411e0..a4c89dba61 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -266,3 +266,9 @@ LDM_t16 1011 110 ......... \ SVC 1101 1111 imm:8 &i B_cond_thumb 1101 cond:4 ........ &ci imm=%imm8_0x2 } + +# Unconditional Branch + +%imm11_0x2 0:s11 !function=times_2 + +B 11100 ........... &i imm=%imm11_0x2