From patchwork Wed Sep 18 14:56:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 11150621 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7C91014ED for ; Wed, 18 Sep 2019 15:52:35 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5D80821907 for ; Wed, 18 Sep 2019 15:52:35 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5D80821907 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:60296 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iAcFt-0004nT-TL for patchwork-qemu-devel@patchwork.kernel.org; Wed, 18 Sep 2019 11:52:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49531) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iAbsW-0007E4-0P for qemu-devel@nongnu.org; Wed, 18 Sep 2019 11:28:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iAbsU-0006t3-Gt for qemu-devel@nongnu.org; Wed, 18 Sep 2019 11:28:23 -0400 Received: from mail-pf1-f177.google.com ([209.85.210.177]:44378) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iAbsU-0006sK-52 for qemu-devel@nongnu.org; Wed, 18 Sep 2019 11:28:22 -0400 Received: by mail-pf1-f177.google.com with SMTP id q21so181492pfn.11 for ; Wed, 18 Sep 2019 08:28:22 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:cc:from:to; bh=tDJG1p1Bp8CpFD/Bq7K8CLsWHyHj5vOvpUlOoU/iQGc=; b=qP6BVdYvGFGgcMkyHxawitzDrCHkxAsbM5jbt0ItVUzls5GgRL+0n9M1Xt0McgsTvE 8CYL20KaNX8g1DXm+Jc8CqAkgCqG32c4a/lRMtW6qEzhbmDWqpNTmrkO8KQqgextjUBK OPwG/VJ3C/GLxY5ZcM+ngj45QgR5NhgnbVUN1NZ1kbV1UR3EEfyIc7hZmCPQEJc8WLkv BMphVVetdVAbBq3IgdbgR7izXW6/WBPjhw+K1bHl8N5dnUpUo0eiuHVELGHGNxsQM1co 6v5w5uecs76vRmEOra6KArWnT/vJwczA7Hw1Uhjm0bIs/Vq3fxqEKha/s8iXwmX+R0cG Pczw== X-Gm-Message-State: APjAAAWi66HNrG8Df4TirBtH0mjINnRVD1Cf50XYKD3A4nWtl/Q9L0kp YQ2eqcBPZdA7linvnBBfuELtnA== X-Google-Smtp-Source: APXvYqy+cRT/+fOnG5BSUB9VolPu2Dcg/rkpD2wAniy3O29vmboPhteFLknO2COjItiyYBPB5syO6w== X-Received: by 2002:a17:90a:bd8a:: with SMTP id z10mr4425137pjr.52.1568820500957; Wed, 18 Sep 2019 08:28:20 -0700 (PDT) Received: from localhost ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id q20sm8662833pfl.79.2019.09.18.08.28.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Sep 2019 08:28:20 -0700 (PDT) Date: Wed, 18 Sep 2019 07:56:17 -0700 Message-Id: <20190918145640.17349-26-palmer@sifive.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190918145640.17349-1-palmer@sifive.com> References: <20190918145640.17349-1-palmer@sifive.com> MIME-Version: 1.0 From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.210.177 Subject: [Qemu-devel] [PULL 25/48] riscv: sifive_e: prci: Update the PRCI register block size X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Palmer Dabbelt , qemu-devel@nongnu.org, Chih-Min Chao , Alistair Francis , Bin Meng Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng Currently the PRCI register block size is set to 0x8000, but in fact 0x1000 is enough, which is also what the manual says. Signed-off-by: Bin Meng Reviewed-by: Chih-Min Chao Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- hw/riscv/sifive_e_prci.c | 2 +- include/hw/riscv/sifive_e_prci.h | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/hw/riscv/sifive_e_prci.c b/hw/riscv/sifive_e_prci.c index bfe9b13a67..a1c0d44f18 100644 --- a/hw/riscv/sifive_e_prci.c +++ b/hw/riscv/sifive_e_prci.c @@ -87,7 +87,7 @@ static void sifive_e_prci_init(Object *obj) SiFiveEPRCIState *s = SIFIVE_E_PRCI(obj); memory_region_init_io(&s->mmio, obj, &sifive_e_prci_ops, s, - TYPE_SIFIVE_E_PRCI, 0x8000); + TYPE_SIFIVE_E_PRCI, SIFIVE_E_PRCI_REG_SIZE); sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); s->hfrosccfg = (SIFIVE_E_PRCI_HFROSCCFG_RDY | SIFIVE_E_PRCI_HFROSCCFG_EN); diff --git a/include/hw/riscv/sifive_e_prci.h b/include/hw/riscv/sifive_e_prci.h index c4b76aa17a..698b0b451c 100644 --- a/include/hw/riscv/sifive_e_prci.h +++ b/include/hw/riscv/sifive_e_prci.h @@ -47,6 +47,8 @@ enum { SIFIVE_E_PRCI_PLLOUTDIV_DIV1 = (1 << 8) }; +#define SIFIVE_E_PRCI_REG_SIZE 0x1000 + #define TYPE_SIFIVE_E_PRCI "riscv.sifive.e.prci" #define SIFIVE_E_PRCI(obj) \