From patchwork Wed Sep 18 14:56:33 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 11150661 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CCFDE1747 for ; Wed, 18 Sep 2019 16:06:40 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id AD031208C0 for ; Wed, 18 Sep 2019 16:06:40 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org AD031208C0 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:60440 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iAcTW-000268-W5 for patchwork-qemu-devel@patchwork.kernel.org; Wed, 18 Sep 2019 12:06:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49918) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iAbsr-0007lS-FD for qemu-devel@nongnu.org; Wed, 18 Sep 2019 11:28:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iAbsp-00078g-St for qemu-devel@nongnu.org; Wed, 18 Sep 2019 11:28:45 -0400 Received: from mail-pg1-f194.google.com ([209.85.215.194]:44614) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iAbsp-00078L-NQ for qemu-devel@nongnu.org; Wed, 18 Sep 2019 11:28:43 -0400 Received: by mail-pg1-f194.google.com with SMTP id i18so26806pgl.11 for ; Wed, 18 Sep 2019 08:28:43 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:cc:from:to; bh=zoTfnPNo+HKyoYh1Fp8HDEvDsUoKiwqregGDjCmxaIA=; b=bDNLTGtHkNxOFQyVbxBgFxZi1lJOLoDR3yVEexWvLXtFU/z+dWyB9sRr+go6Iit7gU s3fcWBlbm4pvXBnlIgVgq9IOMqgtVICwjUIHc9rayzeXns29SBOA4/w8ikWcRN7u8BBG 7dNy8QP6lTKWiRUL4AavxRUPb7v6tD+qBM3eZgru8M2tL/rj7iDVpT+E7bZCLGDxVMFE RRXbOrG9Y8je1uI77fC9mG1TgY/F6gxuqTdyx7Q6Ype8A/cC2inh0Sib2xvoOpfk/Lxr krhyzebSPt7aBPCgAo2NgfHWXOZEJeN2Rd7OJKPl5hE2vmVnX1+GsyCCBxmDjMINV1Jn Ltew== X-Gm-Message-State: APjAAAVm1hQ7eAEduKhVWTzeUz0Z+TJF7bI6xJclW1ViKRPABeglCZ+x LLRwCm3+rhp5qASAEWmIs9y72g== X-Google-Smtp-Source: APXvYqyMsaKhmUbCXAf9TQciQDi4MI6xYzyllKPq4Io0+dtQffhbMUhHWb2uDT8XEGCj2cYoly3v+g== X-Received: by 2002:a17:90a:1b48:: with SMTP id q66mr4416574pjq.79.1568820522421; Wed, 18 Sep 2019 08:28:42 -0700 (PDT) Received: from localhost ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id 16sm5728461pgp.23.2019.09.18.08.28.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Sep 2019 08:28:41 -0700 (PDT) Date: Wed, 18 Sep 2019 07:56:33 -0700 Message-Id: <20190918145640.17349-42-palmer@sifive.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190918145640.17349-1-palmer@sifive.com> References: <20190918145640.17349-1-palmer@sifive.com> MIME-Version: 1.0 From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.215.194 Subject: [Qemu-devel] [PULL 41/48] riscv: sifive_u: Instantiate OTP memory with a serial number X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Bin Meng , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Palmer Dabbelt Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng This adds an OTP memory with a given serial number to the sifive_u machine. With such support, the upstream U-Boot for sifive_fu540 boots out of the box on the sifive_u machine. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- hw/riscv/sifive_u.c | 9 +++++++++ include/hw/riscv/sifive_u.h | 3 +++ 2 files changed, 12 insertions(+) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 24f8c19eee..f5f0c3cbb2 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -10,6 +10,7 @@ * 1) CLINT (Core Level Interruptor) * 2) PLIC (Platform Level Interrupt Controller) * 3) PRCI (Power, Reset, Clock, Interrupt) + * 4) OTP (One-Time Programmable) memory with stored serial number * * This board currently generates devicetree dynamically that indicates at least * two harts and up to five harts. @@ -64,10 +65,12 @@ static const struct MemmapEntry { [SIFIVE_U_PRCI] = { 0x10000000, 0x1000 }, [SIFIVE_U_UART0] = { 0x10010000, 0x1000 }, [SIFIVE_U_UART1] = { 0x10011000, 0x1000 }, + [SIFIVE_U_OTP] = { 0x10070000, 0x1000 }, [SIFIVE_U_DRAM] = { 0x80000000, 0x0 }, [SIFIVE_U_GEM] = { 0x100900FC, 0x2000 }, }; +#define OTP_SERIAL 1 #define GEM_REVISION 0x10070109 static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, @@ -422,6 +425,9 @@ static void riscv_sifive_u_soc_init(Object *obj) sysbus_init_child_obj(obj, "prci", &s->prci, sizeof(s->prci), TYPE_SIFIVE_U_PRCI); + sysbus_init_child_obj(obj, "otp", &s->otp, sizeof(s->otp), + TYPE_SIFIVE_U_OTP); + qdev_prop_set_uint32(DEVICE(&s->otp), "serial", OTP_SERIAL); sysbus_init_child_obj(obj, "gem", &s->gem, sizeof(s->gem), TYPE_CADENCE_GEM); } @@ -498,6 +504,9 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp) object_property_set_bool(OBJECT(&s->prci), true, "realized", &err); sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_PRCI].base); + object_property_set_bool(OBJECT(&s->otp), true, "realized", &err); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_OTP].base); + for (i = 0; i < SIFIVE_U_PLIC_NUM_SOURCES; i++) { plic_gpios[i] = qdev_get_gpio_in(DEVICE(s->plic), i); } diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index 7dfd1cb22e..4d4733cb6a 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -23,6 +23,7 @@ #include "hw/riscv/riscv_hart.h" #include "hw/riscv/sifive_cpu.h" #include "hw/riscv/sifive_u_prci.h" +#include "hw/riscv/sifive_u_otp.h" #define TYPE_RISCV_U_SOC "riscv.sifive.u.soc" #define RISCV_U_SOC(obj) \ @@ -39,6 +40,7 @@ typedef struct SiFiveUSoCState { RISCVHartArrayState u_cpus; DeviceState *plic; SiFiveUPRCIState prci; + SiFiveUOTPState otp; CadenceGEMState gem; } SiFiveUSoCState; @@ -60,6 +62,7 @@ enum { SIFIVE_U_PRCI, SIFIVE_U_UART0, SIFIVE_U_UART1, + SIFIVE_U_OTP, SIFIVE_U_DRAM, SIFIVE_U_GEM };